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442 Discussions

SignalTap influences the designed timing?

BazingaWei
Novice
419 Views

i'm using SignalTap by debugging the design, when i compile the design with SignalTap, all timing is correct and the waveform shown by SignalTap GUI is perfect. BUT when i disable the SignalTap in the project and recompile the design, timing not met and the output of design is wrong.

is there anyone who knows what's going on here?

 

Regards

0 Kudos
1 Solution
KennyT_Intel
Moderator
350 Views

Thanks for your feedback,


As mention previously, you have to treat signaltap as any logic inside the fpga. Which means adding a signal tap equivalent to add extra custom logic to your design.


Sometimes, add additional logic will lead to timing closure and vice versa. If you need help for us to dive into it. You may have to send us a design.qar to look into it.


Another way to close this type of timing is use DSE. https://www.youtube.com/watch?v=1cc74E3zaeI since you have a design with timing close before.


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8 Replies
KennyT_Intel
Moderator
398 Views

You may have to treat signaltap as any logic inside the fpga for that is what it is. 


The timing must not be violated after removing the signal tap or else your output would be unreliable. 


Usually, signal tap will add more logic towards it and removing will ease the timing. You may have to analyze your design again.



BazingaWei
Novice
393 Views

Thanks for reply.

I haved analyzed my design and found something else. I implemented TDC on Cyclone IV, the designed carry chain is enough long for clock period, logically by timing report, the setup time for some registers will be not met. The problem is, when i compile with SignalTap, the setup time reported in worst-case given by the Timequest Timing Analyzer is about 'altera_reserved_tck' and no other warnings or errors, this 'altera_reserved_tck' comes from JTAG, if i'm correct, but it's not the desired timing report about my design. (ps:without SignalTap the timing report is correct)

So, is there any way to get the wanted timing report from full compilation with SignalTap?

Another question is, is that correct that the delay for odd-indexed delay cell is enormously larger than the even-indexed delay cell? For example, the delay for first cell is much larger than the second one.

 

Best Regards

KennyT_Intel
Moderator
374 Views

You may refer to here


https://www.researchgate.net/publication/283355482_New_Design-methodology_of_High-performance_TDC_on...


Basically, you will have to try to control location of the register for TDC implementation.


BazingaWei
Novice
371 Views

Hi, KennyT_intel, thanks for the reply, the reference is helpful, but it is not to my question. I implemented TDC on my device, my question is about Timequest. I show you some figures to make my question clear.

Case 1, compile the whole project without signaltap, i got following report from Timequest Timing Analyzer:

fig1.png

Case 2, compile the whole project with SignalTap, i got following report from Timequest Timing Analyzer:

fig2.png

The two reports differs a lot, my question is why this happens, why there are no 'Warnings' at Worst-Case Timing Paths and What kinds of role does signaltap plays?

Anyway, thanks for reply!

Best Regards

KennyT_Intel
Moderator
351 Views

Thanks for your feedback,


As mention previously, you have to treat signaltap as any logic inside the fpga. Which means adding a signal tap equivalent to add extra custom logic to your design.


Sometimes, add additional logic will lead to timing closure and vice versa. If you need help for us to dive into it. You may have to send us a design.qar to look into it.


Another way to close this type of timing is use DSE. https://www.youtube.com/watch?v=1cc74E3zaeI since you have a design with timing close before.


View solution in original post

KennyT_Intel
Moderator
339 Views

Any further queries on this?


BazingaWei
Novice
334 Views

Hi, KennyT_intel,

thanks for helping me, i have no more questions.

Best Regards

KennyT_Intel
Moderator
300 Views

Since there are no more question, closing the thread. If you have further queries, kindly post a response in the next 15 days.

After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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