Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
606 Discussions

Which IP Category is recommended for the Math Square Root function?

shriram_INTL
Employee
607 Views

Hi 

I'm looking for assistance in creating an IP for the square root function. At the moment, I only have square root Verilog code. I'm looking for recommendations for FPGA, I/O Chip, and SDC using Quartus Prime Pro.

 

Thanks and best regards,

Sriram

0 Kudos
1 Solution
ShengN_Intel
Employee
473 Views

Hi Shriram,

 

However, I'm having issues with timing and I/O chip placement. Any suggestions?

Timing issues had been resolved by sdc file. I reattached the file below with new sdc as I further remove the unconstraint paths. As for I/O chip placement you may have to open a new thread in FPGA, SoC, And CPLD Boards And Kits forum for better confirmations.

 

How to calculate / how to find speed grade around for a clock in MHz ?

The clock frequency can be checked in timing analyzer by report clock. As for speed grade you can refer to this document https://my.mouser.com/datasheet/2/612/s10_datasheet-1652682.pdf Core Performance Specifications section (page 28).

 

How to determine Maximum combined path delay in ns ? 

Can be checked in timing analyzer as well by report timing.

 

Hope it helps. Thanks.

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

View solution in original post

6 Replies
ShengN_Intel
Employee
540 Views

Hi,


FPGA - Can refer https://www.intel.com/content/www/us/en/docs/programmable/683339/21-3-19-1-1/fixed-point-ips-device-family-support.html for device support list.

I/O Chip - Do you mean processor?

SDC - Do you mean Scalable Dataframe Compiler or Synopsys Design Constraints?


Best Regards,

Sheng


shriram_INTL
Employee
528 Views

Hi Sheng

I am using Intel® Stratix® 10. 

I/O Chip is the 1SG280LN2F43E1VG

SDC mean Synopsys Design Constraints

I can successfully compile the design with above attached files.

 

However, I'm having issues with timing and I/O chip placement. Any suggestions?

  1. How to  calculate / how to find speed grade  around for a clock in MHz ?
  2. How to determine Maximum combined path delay in ns ? 

 

Following Critical Warning are reported 

  • Critical Warning(20615): Use the Reset Release IP in Intel Stratix 10 FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Intel Stratix 10 Configuration User Guide.
  • Critical Warning(12677): No exact pin location assignment(s) for 34 pins of 34 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report
  • Critical Warning(332012): Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
  • Critical Warning(19527): There are 48 unused RX channels and 48 unused TX channels in the design.
  • Critical Warning(332012): Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
  • Critical Warning(332012): Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
  • Critical Warning(19317): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
  • Critical Warning(332148): Timing requirements not met
  • Critical Warning(332012): Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
  • Critical Warning(19317): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
  • Critical Warning(19238): Incomplete power management settings for a VID device. As a result, the tool may not generate device bitstream.
  • Critical Warning(19239): Missing required setting "SDM PWRMGT SCL output"
  • Critical Warning(19239): Missing required setting "SDM PWRMGT SDA output"
    Critical Warning(19239): Missing required setting "PMBus device 0 slave address"

Timing Analysis Error 

  • Synopsys Design Constraints File file not found: 'mlhdlc_sqrt.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
  • No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
  • Timing requirements not met

Thank you

Shriram

 

 

ShengN_Intel
Employee
495 Views

Hi Shriram,

 

I have created a sdc file for the design to solve the timing requirements not met issue. The file is attached below for your reference.

 

These two critical warnings below can be ignored if you don't intend to use them.

Critical Warning(20615): Use the Reset Release IP in Intel Stratix 10 FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Intel Stratix 10 Configuration User Guide. 

Critical Warning(19527): There are 48 unused RX channels and 48 unused TX channels in the design. 

 

As for these five critical warnings below may be you have to open a new thread in FPGA, SoC, And CPLD Boards And Kits forum for better guidance and confirmations.

Critical Warning(12677): No exact pin location assignment(s) for 32 pins of 32 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report 

Critical Warning(19238): Incomplete power management settings for a VID device. As a result, the tool may not generate device bitstream. 

Critical Warning(19239): Missing required setting "SDM PWRMGT SCL output" 

Critical Warning(19239): Missing required setting "SDM PWRMGT SDA output" 

Critical Warning(19239): Missing required setting "PMBus device 0 slave address" 

 

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

shriram_INTL
Employee
490 Views

Hi Sheng

I have created a sdc file for the design to solve the timing requirements not met issue. The file is attached below for your reference.

Sorry , I don't see the attachment !! I am I missing . sorry for the trouble.

 

Any feedback for below question

However, I'm having issues with timing and I/O chip placement. Any suggestions?

  1. How to  calculate / how to find speed grade  around for a clock in MHz ?
  2. How to determine Maximum combined path delay in ns ? 

 

best regards,

Sriram

ShengN_Intel
Employee
474 Views

Hi Shriram,

 

However, I'm having issues with timing and I/O chip placement. Any suggestions?

Timing issues had been resolved by sdc file. I reattached the file below with new sdc as I further remove the unconstraint paths. As for I/O chip placement you may have to open a new thread in FPGA, SoC, And CPLD Boards And Kits forum for better confirmations.

 

How to calculate / how to find speed grade around for a clock in MHz ?

The clock frequency can be checked in timing analyzer by report clock. As for speed grade you can refer to this document https://my.mouser.com/datasheet/2/612/s10_datasheet-1652682.pdf Core Performance Specifications section (page 28).

 

How to determine Maximum combined path delay in ns ? 

Can be checked in timing analyzer as well by report timing.

 

Hope it helps. Thanks.

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

shriram_INTL
Employee
449 Views

Hi Sheng,

Thank you so much, Sheng!!

Could you tell me your employee number or name? I'd like to seek a brief meeting for further explanation

best regards,

Sriram

Reply