I plan to use 10M25DC FPGA for to drive 7mA load @3.3V. As per MAX 10 General purpose I/O user guide, 3.3VLVTTL only have capability to drive 8mA(3.3V LVCMOS is 2mA maximum). Kindly correct me if I am wrong also reply below queries.
1.For IOH=-8mA,What will be the VOH(min) and VOL(Max) values?For 4mA,Voh(min)=2.4V, Vol(max)=0.45V is found from datasheet. whether this value can i use for IOH=-8mA?
2.Also the logic level 3.3V LVTTL and 3.3LVCMOS can i set for induividual pins?Or for each bank do i need to set either LVTTL or LVCMOS?
Kindly consider this as urgent and reply.
IOH and IOL values that in the datasheet are not max values, but recommended ones and are based on JEDEC standards.
For your application, you can use 3.3V LVTTL, 8mA setting in Quartus.
VOHmin and VOLmax remains same for all the IOL and IOH settings.
3.3V LVTTL and 3.3LVCMOS levels can be set for individual pins in a bank.
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