Can someone please explain me the Duty Cycle of IA32_CLOCK_MODULATION MSR ?

[Alam__Shariful]

I'm a novice. So if this question doesn't make any sense, please excuse me. I'm looking into the Intel Software Developer’s Manual and come across this IA32_CLOCK_MODULATION MSR. In the description table of On-Demand Clock Modulation Duty Cycle Field Encoding, it shows a different percentage of Duty Cycle for different Duty Cycle Field Encoding. So, my question is what do those percentages (%) mean. Does it mean that, for example, setting Field as 010B, I'm using 25% of the processor's available cycle?    

[McCalpinJohn · Accepted solution]

With "duty cycling", the clock signal is not passed to the processor core every cycle.  Since the processor core only does things when it receives a clock signal, this reduces the effective clock rate of the core.  "Clock modulation", which allows you to specify what fraction of "normal" cycles send the clock signal to the core.  Newer processors support the extended clock modulation.  The bottom 4 bits of the IA32_CLOCK_MODULATION MSR tell how many cycles (out of 16) will send the clock signal to the processor core.   So for 010b, the processor core will receive the clock signal 4 times out of every 16 cycles, and it will therefore appear to be operating at 1/4 of the clock frequency.

[Alam__Shariful]

Thank you very much.  

[Alam__Shariful]

One last question. If I change the bottom 4 bits of the IA32_CLOCK_MODULATION MSR, does it change cycle for all the available core? If yes, is there any way to change the cycle for a particular core? 

[McCalpinJohn]

This is documented in Volume 3 of the Intel Architectures SW Developer's Manual: Section 14.7.3 "Software Controlled Clock Modulation"

"For multiple processor cores in a physical package, each processor can modulate to a programmed duty cycle independently."

[jimdempseyatthecove]

>>The bottom 4 bits of the IA32_CLOCK_MODULATION MSR tell how many cycles (out of 16) will send the clock signal to the processor core.   So for 010b, the processor core will receive the clock signal 4 times out of every 16 cycles, and it will therefore appear to be operating at 1/4 of the clock frequency.

Did you mean to say 0100b?

And I assume a value of 0000b provides for 16 times out of every 16 cycles. (IOW 0000b indicates no modulation)

Jim Dempsey

[McCalpinJohn]

The '010b' is the encoding for the "non-extended" version -- bits 3:1 -- where it provides the active count for eight cycle blocks.  

This expands to '0100b' in the extended mode -- which uses bits 3:0 -- where it represents the active count for sixteen cycle blocks.

Section 14.7.3 of Volume 3 of the SWDM says that '000b' is reserved in the base (eighths) mode and '0000b' is reserved in the extended (sixteenths) mode.  So the implementation can do whatever it wants if you set the enable bit, but leave all the duty cycle bits clear.