Does a cache line prefetched in the RTM region will evict some cache line in the read set or write set and cause the transaction abort ?
Thanks for your reply. Does the some prefetch policy like adjacent cache lline prefetch will also evict a cache line already in the write set?
And do you have any idea about how to disable the hardware cache prefetcher? I try to disable haswell cache prefetcher, but there is no options in the BIOS. I also can't find any msr bit can be used to disable the cache prefetcher in the SDM for the haswell.
Unfortunately the MSRs used to disable various prefetchers are different for each Intel processor family, and documentation is not available in public documents. In many cases, some or all of the hardware prefetchers can be disabled through the BIOS, but this is not a required feature.