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SDM mentions states of the access rights in GDTR and IDTR, but they are do not have that concept

Tanda__Satoshi
Beginner
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Table 9-1. IA-32 and Intel 64 Processor States Following Power-up, Reset, or INIT (Contd.) describes state of GDTR and IDTR as below, 

Base = 00000000H
Limit = FFFFH
AR = Present, R/W

But AR = Present, R/W are not applicable to those two registers. 

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