Does SFENCE(MFENCE) instruction ensure that preceding memory writes are actually propagated to the system bus, so the writes are visible by bus master peripheral devices? Or does it work in conjunction with MESI protocol and is guaranteed to propagate writes only between CPUs/cores?
We forwarded this question to our engineering contacts,one of whomresponded:
sfence does cause the so called "PCI posting" to be flushed to devices. The most common way to force a PCI posting flush is to do an mmio read from the device in question; per the PCI spec this will cause any buffered (posted) data to be flushed first.