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I see here: https://en.wikipedia.org/wiki/Intel_SHA_extensions that these instructions became available on the Goldmont micro-architecture. That wikipedia page was last edited on February 10, 2016, but this page https://en.wikipedia.org/wiki/Goldmont_(microarchitecture) states that Goldmont was unveiled at the Intel Developer forum in April, 2016, and Intel documentation dates back to 2013. I used this function
int CheckForIntelShaExtensions() { int a, b, c, d; // Look for CPUID.7.0.EBX[29] // EAX = 7, ECX = 0 a = 7; c = 0; asm volatile ("cpuid" :"=a"(a), "=b"(b), "=c"(c), "=d"(d) :"a"(a), "c"(c) ); // Intel® SHA Extensions feature bit is EBX[29] return ((b >> 29) & 1); }
to determine that my Broadwell-U Intel Core i7 5500U does NOT support the SHA Extensions.
So I would like to confirm which micro-architectures will actually support these instructions.
Thanks.
- Tags:
- Intel® Advanced Vector Extensions (Intel® AVX)
- Intel® Streaming SIMD Extensions
- Parallel Computing
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I've only seen unofficial information that SHA extensions will be first present in Cannonlake. http://wccftech.com/mainstream-intel-core-processors-support-avx-512-skylake-xeon/
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