Was Hardware Lock Elision completely broken by TAA mitigation?

[Guteniev__Alex]

I'm referring to this:

Intrinsics for Hardware Lock Elision Operations

Were these instructions completely broken due to TAA mitigation for all the CPUs?

Are they never coming back?

(Should the documentation be updated to reflect the state?)

[Guteniev__Alex]

I've read this page:

Intel® Transactional Synchronization Extensions (Intel® TSX) Asynchronous Abort / CVE-2019-11135 / INTEL-SA-00270

But it is still not clear:

1. Was HLE unconditionally disabled or there are options to enable it?

2. Are there any current or future CPUs that enable it?