gather instructions and the size of indexs for a given base gpr size

[perfwise]

Hi,

    I have a simple question.  When performing address computations, the size of the BASE and the INDEX are required to be the same.  I presumed this was the case in the GATHER instructions.. but I don't believe it is so now.  Can someone confirm?  Namely.. I'm asking if you can use a 64-bit gpr BASE register, and use 32-bit indexes in an instruction like VGATHERDPS or VPGATHERDD.  In these 2 instructions the indexes are 32-bit values, which I presume are sign extended to 64-bits when you have a 64-bit gpr BASE specified.  I didn't find it clearly stated this was possible nor did I find it was prohibited.. so just wanted to clarify.  

Thank you for any helpful and concise feedback

perfwise

[jimdempseyatthecove]

Base is a pointer contained in a general purpose register (64-bit in 64-bit mode).

Search for:

      Intel Advanced Vector Extensions Programming reference site:intel.com format:.pdf

Jim Dempsey

[perfwise]

Jim,

    I know the BASE is a gpr register.  My question was .. is there a restriction that the size 32-bits or 64-bits of the base register match the size of the index in the VSIB xmm or ymm register?  Can I use a 64-bit gpr for the base and 32-bit indices for the indexes in the VSIB?  Thanks..

perfwise

[jimdempseyatthecove]

No. It is more of the case that the index size match the data element size in the vector register. In regards to scatter/gather

If you fetch QWORDS (DP) using QWORD indices you can fetch the full vector width.
If you fetch DWORDS (SP) using QWORD indices you have half the number of indices as you have DWORDS in the vector, therefor you can only fetch half the vector (remainder gets zeroed).
If you fetch DWORDS (SP) using DWORD indices you can fetch the full vector width.
At present, if you want to gather WORDS or BYTES, you have to gather them as DWORDS (however this has alignment restrictions).

The base register (64-bits) (plus offset if any) specifies the origin for the indexing.

Jim Dempsey

[MarkC_Intel]

No restrictions on the widths of the base vs widths of the index elements. The SDM says bits will be ignored if the (scaled) index is wider than the addressing mode.  Using a 64b base reg with 32b indices is expected to be common if the indices are offsets in to an array. 

[perfwise]

Thanks Mark.  That's what I was inquiring about.  Naively I assumed the indices had to be the same size as the base, but that doesn't appear to be the case.  Very useful instruction.

perfwise