We are using Intel IPP library version 5.3. And facing a problems on AMD processors with SSE4a instruction set.
Wich version of IPP library supports this instruction set? How to get this version (what is licensing policy)?
Please read this KB article for detailed information regarding the SIMD instructions supported by the Intel IPP library, through version 6.1.
Understanding CPU Dispatching in the Intel IPP Library
Note that most AMD and Intel processors produced today support the SSE2 and SSE3 instruction sets. The SSE4a instruction set is unique to AMD processors and is not supported by the Intel IPP library. As you can see from the chart in the table above, after SSE3, the library supports the SSSE3, SSE4.1, SSE4.2, AES-NI and AVX instruction sets.
There are also several good articles in Wikipedia describing the differences between the various SIMD instructions sets available today.
Regarding licensing, please review the following KB articles:
Location of the End User License Agreement (EULA)
How do I renew my license?
Development Products Download, Registration and Licensing Help
Intel IPP Downloads, Registration and Licensing
Which Intel IPP libraries are "Redistributables"?
Intel Integrated Performance Primitives - Licensing FAQ
In essence, you pay a license, per developer, to download and use the IPP library to create an application. There are no royalties associated with distribution of your IPP application. That is, you do not pay any license fees to redistribute an application you build with the IPP library. The specific files you may redistribute with your application are described in the "redist.txt" file that is part of the development package.
Thanks for your reply!
We have rebuilt our projects with Intel IPP v 6.1, but haven't tested them on AMD processors yet. Howerer, it appears, that the possible problem we've faced will remain.
This is basically that Intel IPP library apparentely misdetects SSE4.1 or SSE4.2 instruction set on the AMD processors with SSE4A instruction set (when dispatching), which seems to crach some code parts (incorrect code execution). As I know, the previous IPP library (5.3) had an opportunity just to enable/disable optimization at all. I wonder if there is a possibility to enable/disable certain instruction sets in Intel IPP 6.1?
As a possible solution, we will detect SSE4A instruction set ourselves and initialize Intel IPP with restrictions on SSE4 instruction sets on AMD SSE4A processors, while disabling optimization at all in such cases doesn't seem good at all.
Reading some links you gave me, I've founded fuctions ippInitCpu and ippEnableCpu. I suspect these functions are to solve the problem.
Or maybe there are some alternatives to avoid misdetection of SSE4 instruction sets on AMD SSE4A?
Thank you very much!
If your code detects a SSE4-supported CPU on an AMD-system, your detection goes wrong, because AMD does not support SSE4 at this moment. They only support an AMD-only subset SSE4a. Intel compatibility only goes to SSE3.
You should also read this thread:
Also, as a debugging aid, compile and run the ippcpuinfo sample (in the advanced-usage samples) and see what it is reporting. The library "recommended" by this application is the one the IPP dispatcher will select.
Another idea: if 10% increase is all you get, it could be because you run on a single-core HT-enabled CPU. Running two threads on such a CPU would not give 2x performance.