The very last sentence on page 7 of the http://www.intel.com/content/dam/support/us/en/documents/edison/sb/edisonaudio_332434001.pdf Edison Audio Setup Guide PDF states:
The audio DSP has to be the master of the bus.
Then on page 9 of the same document it repeats at the top:
The following restrictions apply: The audio DSP has to be the master of the bus.
Yet Edison doesn't output any audio master clock, which most oversampling converters on the market accept at x256 the sampling frequency and higher. A handful of consumer/mobile oriented audio codecs exist that feature a PLL to generate its master clock from incoming I2S signals. These devices are mostly available in BGA/CSP packages, making them useless for hobbyists which I would assume the Edison board is partially targeting as their market. )
Since, as stated above, the SSP port has to be the master, then using a crystal on the audio codec's end for precision x256 master clock is out of the question, isn't it? Then how does one generate an audio-grade 12.288MHz clock (x256 of 48kHz) if a codec is a slave?
This has been puzzling me for a few days now, maybe I'm way off, but please enlighten on how to interface the Edison board with codecs such as PCM3168, CS42448, AK4612, and alike. Thank you!
Thank you for waiting, after investigating on your case, the update we can provide is that the Edison has a standard I2S interface without the optional outputs. At this time Edison does not provide a MCLK. For this case, we would need you to select an audio codec with an internal PLL circuit or implement a standalone PLL.
Let us know if there's anything else we can assist you with.