We've created a custom carrier board for the Joule, and are tying to use the PCIe to connect to an FPGA. It seems as though we're unable to get the Joule to use the PCIe pins for PCIe, rather than USB3. I imagined that this ought to be a BIOS setting, but I can't find a setting for it.
- I'm seeing the 100 MHz clock when I assert CLK_REQUEST# . This seems good.
- The FPGA board has been tested with other PCIe Root Ports and definitely works. This proves the system fundamentally works.
- I ensure that the FPGA is loaded before powering on the Joule to ensure that the endpoint is present when it scans the bus.
Things I've tried:
- In the Firmware I've gone into Device Manager -> System Setup -> South Cluster Configuration -> PCI Express Configuration -> PCI Express Root Port (2 or 1) and set them both to from
- Enabling/Disabling Hot Plug
- Under ACPI Settings, "Native PCIE Enable" is
Any help would be greatly appreciated.
I'm attaching an alternate firmware for the Joule that changes the MUX on the PCIe/USB3 pins.
This worked on my custom board, but I make no guarantees that it will work for anyone else, and am not going to be able to support it in any way. If you want to be able to modify the firmware for your own custom applications, you need to get access to Intel's TXE kit through their Validation Internet Portal.
Thanks for your interest in the Intel Joule Platform.
I'm sorry to hear that you can't connect a FPGA to your Intel Joule by PCIe. Just to be sure, are you connecting your PCIe correctly? Please see the image attach below. Also the PCIe is multiplexed with the USB3 in Port 1, you have to make sure that you are selecting the PCIe.
I will be waiting for your reply, have a nice day.
I'm fairly certain that I've connected the PCIe correctly. And I do see the 100mhz clock when the clock request pin is pulled low. Adidtionally, PERST_N is going high on boot as it should. I'm not using Wake_n, which should be fine according to the PCIe spec, since it's only to request the CPU wakes up. I added a pull down to it just in case.
I'm not sure where to select PCIe rather than USB 3, since there doesn't seem to be any settings in the BIOS to change the pin mux. Even when I set the settings that I found in my original post, it doesn't change anything.
Interestingly, if I plug the Joule back into the developer kit, the USB 3 still works (as super-speed USB, not just as USB 2), so I know for sure that the pins aren't getting mux'd to PCIe. This means that some unrelated to my custom PCB is wrong.
Where should I be looking to set those pins to PCIe instead of USB? I can't find documentation for that anywhere on the Joule site.
After some investigation I realized that the PCIe can only be enabled by using a different BIOS, this PCIe BIOS is not currently available and there is no committed time frame for when it will be accessible. I know this not the answer you were expecting, but maybe you can try communicating to the FPGA using another interface.
That's really disappointing to hear. Unfortunately there isn't another interface that will meet the requirements of this link.
Is there any chance of either:
- Getting access to a pre-release BIOS that gives me these settings?
- Getting access to tools that would allow me to reprogram the SPI/SMIP to have the settings I need?
I'm looking back at the Joule's page <<a href="https://software.intel.com/en-us/iot/hardware/joule" title="https://software.intel.com/en-us/iot/hardware/joule">The Intel® Joule™ Compute Module | Intel® Software > and two things jumped out at me:
- It seems like the BIOS is supposed to be open-source. Can get the source to try and update the BIOS to support PCIe?
- PCIe is listed as a supported feature on both the website and the data sheet, not a "release pending" feature, such as the GPIO remapping (as listed in the data sheet revision 1.1 section 2.2). Perhaps an update to the data sheet and website would be good so that other people don't also create carrier boards dependent on unsupported features?
Also, reading through documentation on the Broxton/Apollo Lake processors, it seems as though I should be able to create my own SMIP using the register map in the SPI/SMIP programming guide (559702) if I have access to the TXE tool kit with the FIT and FPT. Is it possible to make that tool available, or is there an alternate way of changing those bits?
Yes the documentation claims that the PCIe is a supported feature, this is not accurate. I will communicate this to the department in charge, I apologize for this.
Now regarding access to the TXE tool kit, I will investigate if this tool is available and I will get back to you as soon as I have some useful information.
Any luck getting the TXE tool kit? Reading around the data sheets for the Broxton Processor, it seems like there are only four SMIP straps that need to be changed:
Thanks for the information provided. We are still investigating if this tool is available, we appreciate your patience.
Have a nice day.
I've now gotten access to the FIT through my account manger. The FIT did allow me to enable the PCIe bus. I how have an alternate firmware binary on my Joules that allows me to use PCIe.
We're still sorting out some stuff with interrupts, but it seems like our PCIe problem should be solved now. If you'd like a copy of the Firmware that supports PCIe, let me know and I can send it to you so that you can provide it to other people with the same issue.
I'm glad to hear that you figure it out by your own! It is not necessary to send it to me, you can share it with the community since it may benefit other users.
We appreciate your contribution!
We hope you have a nice day!
You will not be able to use the normal breakout board from Intel to do PCIe.
Also, with this replacement Firmware, the type A USB3 port will no longer function as a super-speed USB port because of the pin mux between that USB port and the exposed PCIe lane. The USB port still functions as a high-speed port (USB 2).