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Novice
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Galileo JTAG TP1 and TP2 for Reset-Break Debug

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Where in the Galileo board V1 and where in the Galileo board V2 can I find these two pins: TP1 and TP2?

They are present on both boards' schematics.

I would like to be able to physically locate them in the boards.

They are directly connected to the PRDY_B and PREQ_B pins of the Quark SoC and are necessary to debug the Chip with a tool such as the ITP-XDP3BR for instance. I want to be able to debug firmware (UEFI) and it is not implemented on the OpenOCD debugger that is currently available for the Galileo.

Thank you.

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Employee
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Re: Galileo JTAG TP1 and TP2 for Reset-Break Debug

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Hi Andromeda,

the issue really is that the Quark system reset is not wired to the 10pin header, so neither ITP-XDP3 or OpenOCD supported probes can do a real reset / break. But we can get close with a soft reset.

First, if you want to use the ITP-XDP3 for debugging then you need this adapter: https://designintools.intel.com/product_p/itpxdp10pinjtagquark.htm https://designintools.intel.com/product_p/itpxdp10pinjtagquark.htm

The "XDP to 10Pin JTAG Adapter". This plugs into the 10 pin header on Galileo and has the 60 pins XDP connector for the ITP-XDP3.

To debug you would then need a JTAG debugger like XDB which is included in Intel® System Studio http://software.intel.com/en-us/intel-system-studio http://software.intel.com/en-us/intel-system-studio.

Now to getting close ...

The current 2014 version can't do this, but the 2015 version does this over OpenOCD. The changes to OpenOCD have not been upstreamed yet so you'll need to use our version. The current Intel® System Studio 2015 BETA already has OpenOCD inside so you can give this a try.

With Intel® System Studio and OpenOCD we cannot do real Reset / Break, but we get close enough for BIOS / UEFI debugging. We don't hit the reset vector everytime but halt the CPU close enough.

If you do try Intel® System Studio 2015 BETA and run into trouble then please use the offered support channels and we'll see that we help you.

/paul

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Employee
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Re: Galileo JTAG TP1 and TP2 for Reset-Break Debug

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Hi Andromeda,

In the Galileo Gen 1 you can find each JTAG pin in the Galileo schematic /servlet/JiveServlet/previewBody/21822-102-4-25114/Galileo Schematic.pdf https://communities.intel.com/servlet/JiveServlet/previewBody/21822-102-4-25114/Galileo%20Schematic.... .

If you go to this document /servlet/JiveServlet/previewBody/21828-102-3-26270/Quark Datasheet Rev02.pdf https://communities.intel.com/servlet/JiveServlet/previewBody/21828-102-3-26270/Quark%20Datasheet%20... in section 3 you will find the ballout of the quark, and directly below that is the ball listings for the pins. PRDY_B is listed as E7 and PREQ_B is listed as B2. You can try to find them in the ballout above and physically access the pins. Let me know if this works.

Regards

Sergio

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Employee
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Re: Galileo JTAG TP1 and TP2 for Reset-Break Debug

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Hi Andromeda,

the issue really is that the Quark system reset is not wired to the 10pin header, so neither ITP-XDP3 or OpenOCD supported probes can do a real reset / break. But we can get close with a soft reset.

First, if you want to use the ITP-XDP3 for debugging then you need this adapter: https://designintools.intel.com/product_p/itpxdp10pinjtagquark.htm https://designintools.intel.com/product_p/itpxdp10pinjtagquark.htm

The "XDP to 10Pin JTAG Adapter". This plugs into the 10 pin header on Galileo and has the 60 pins XDP connector for the ITP-XDP3.

To debug you would then need a JTAG debugger like XDB which is included in Intel® System Studio http://software.intel.com/en-us/intel-system-studio http://software.intel.com/en-us/intel-system-studio.

Now to getting close ...

The current 2014 version can't do this, but the 2015 version does this over OpenOCD. The changes to OpenOCD have not been upstreamed yet so you'll need to use our version. The current Intel® System Studio 2015 BETA already has OpenOCD inside so you can give this a try.

With Intel® System Studio and OpenOCD we cannot do real Reset / Break, but we get close enough for BIOS / UEFI debugging. We don't hit the reset vector everytime but halt the CPU close enough.

If you do try Intel® System Studio 2015 BETA and run into trouble then please use the offered support channels and we'll see that we help you.

/paul

View solution in original post