We just built 75 Edison carrier boards and neglected to connect the SD_0_CLK_FB pin. Is there any way we can configure a Linux kernel to enable access to the SD_CARD without this pin connect? Even if we need to limit the access speed, that would be better than respinning the boards.
Any help or suggestions would be greatly appreciated.
We don't have any updates yet. We're still researching about your case. We'll post here once we have new information to share. Thank you for your understanding.
We are not aware of any kernel configuration to enable access to the SD Card without using the clock feedback signal. This signal is necessary for re-synchronizing data to the processor, you could attempt to do a hardware workaround on your custom boards and somehow enable this connection.
We discussed reworking our 75 boards and simply wiring the feedback signal to the clock signal. That would not account for the propagation delay through the TXS0206. Depending on the clock speed at which the SDIO interface is run, this could work.
How can we limit the maximum clock frequency for the SDIO interface on the Edison?
Is it possible (under NDA if necessary) to obtain the datasheet for the for SoC used on the Edison board?
Thank you very much for your reply.
I've passed your request to get an NDA to the team in charge. I'll contact you as soon as I receive a response. Thank you for your patience.
Thank you for your patience in the matter. We received a response about the SoC datasheet and it is not publicly available, even if under an NDA. We appreciate your understanding.
We've done the proper research and reached the conclusion that it's only possible to access the SD card with SD_O_CLK_FB connected. We received, however, a message from the hardware team that suggests you to respin your board.
Hopefully you find this useful.
Please let us know if there's something else we can help you with.
I think it might be possible to (semi-) work around this. So, CLK signal still needs to be connected to one of free GPIO pins and driver should use kinda bitbanging protocol. Unfortunately I have no idea if it's allowed by SD standard to have OOB clock signal.
So, I agree that correct answer rather to reissue new PCB design.