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TEarl1
Novice
1,364 Views

JTAG (IEEE 1149.1) instructions for Quark D2000

Hi everyone,

I'm building a custom debugger for Quark processors and am looking for its IEEE 1149.1 (JTAG) boundary scan instruction codes.

Reading through the D2000 Debug Operations User's Guide, I found its BYPASS and IDCODE and USERCODE instruction codes. But I don't see a number of the other mandatory JTAG codes (or optional JTAG codes). The document does say that the Quark D2000 is IEEE 1149.1a-1993 compliant so the codes should be documented, but I'm not sure where to look.

Does anyone know where I can find documentation on the instruction codes (and any associated details) for the JTAG-mandatory EXTEST, PRELOAD and SAMPLE instructions? For those unfamiliar with JTAG, these codes are mandatory but each manufacturer chooses their own values for the instruction codes.

Also, are any of the optional JTAG instructions (INTEST, RUNBIST, CLAMP or HIGHZ) implemented? I know that a few of those were added to JTAG after the 1993 standard.

Hopefully what I'm building will be really useful to the maker community and some pros as well. It's hopefully going to be a really cool cross-platform debugger for Quark processors.

Tandy

3 Replies
Pedro_M_Intel
Employee
70 Views

Hello Tandy,

Thanks for reaching out!

Please let us investigate about this. If I'm able to find some useful information regarding this I will make sure to post it here.

-Peter.

70 Views

Hi Tandy,

While EXTEST, PRELOAD, SAMPLE instructions are "JTAG instructions" that OpenOCD supports, the "D2000 Debug Operations User's Guide" only covers the instructions for debugging/development, not including the ones you mentioned that are more like used for manufacturing tests. I'd need to check whether we can disclose further info on the values used for EXTEST etc and will get back to you shortly.

Regards,

Alex

TEarl1
Novice
70 Views

Hi Alex,

Thanks for your help on this.

I would assume that a lot of your customers use boundary scan during PCB assembly as a way to detect solder shorts between IO pins, to ensure that balls were attached to the board properly, etc. So hopefully this is info that can be provided--or we'll be relying on AOI (automated optical inspection) and xray processes instead (especially when it comes to the BGA chips where the pins aren't visible).

Thanks again,

Tandy

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