LLVM compiler backend for Quark SE C1000's DSP (ARCv2)?

[TEarl1]

Hey everyone,

I'm working on a really exciting hobby-and-commercial project with Quark SE C1000, and want to take advantage of the Quark SE C1000's second processor (the ARCv2 DSP core).

I'm working with an LLVM compiler front-end, but I haven't been able to track down an ARCv2 compiler backend for ARCv2 quite yet.

What are you guys doing to take advantage of the chip? I'd use GCC for this, but there are some GPL licensing concerns there (esoteric linking concerns) so I'm hoping someone knows of an LLVM back-end that can take advantage of this awesome second processor.

[ Intel--do you have something available? Need help getting something bootstrapped? I've built compilers in the past ]

Thanks everyone,

Tandy

[Michelle_C_Intel]

The ISSM Toolchain currently includes following compilers for Quark SE C1000

QMSI(Bare Metal) - GCC-IA for the x88 core

GCC-ARC for the ARC core

Zephyr RTOS - GCC-IA & LLVM-IA for the x86 core

GCC-ARC for the ARC core

-- Michelle.

[TEarl1]

Hi Michelle,

For LLVM (Zephyr RTOS), what CLANG and LLC command-line arguments do you recommend using for Quark D2000 and Quark SE C1000? Which triplet should we use? Is "-mcpu=lakemont" the only argument required for llc?

I found the original Lakemont LLVM check-ins based on the following Intel presentation--but it does not provide any sample or recommended command-line arguments.

http://www.llvm.org/devmtg/2016-03/Presentations/X86CodeSizePDF.pdf http://www.llvm.org/devmtg/2016-03/Presentations/X86CodeSizePDF.pdf

https://www.youtube.com/watch?v=yHexQSFud3w&feature=youtu.be 2016 EuroLLVM Developers' Meeting: Z. Ansari & D. Kreitzer "Improving LLVM Generated Code Size ..." - YouTube

Thanks!

Tandy