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Beginner
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Quark C1000 QMSI v1.4.0 SPI interface problem

Hi ALL:

I used Quark C1000 (QMSI 1.1) to read/write a LoRa module with SPI interface. (ISSM version: ISSM_2016.1.067)

In QMSI 1.1, my program workable. I can read/write data via SPI-1 interface to control LoRa module.

Recently, I got new ISSM (ISSM version: ISSM_2016.2.090), it support QMSI v1.4.0.

So, I'm Update ROM with my CRB and testing with this version.

But, I have a problem at SPI interface to read/write data.

If I configure GPIO2 (AP_GPIO2_ADC2_SPI_S_SCLK) as output pin. Then SPI interface can't read/write data.

Example:

qm_gpio_port_config_t cfg;

/* Request IRQ and write GPIO port config. */

//cfg.direction = BIT(2)|BIT(4)|BIT(5)|BIT(6)|BIT(7); <=== if use this line , SPI-1 interface can't read/write data.

cfg.direction = BIT(4)|BIT(5)|BIT(6)|BIT(7); <=== if NO GPIO 2, SPI -1 interface can use.

cfg.int_en = BIT(QM_PIN_ID_3); /* Interrupt enabled. */

...

qm_gpio_set_config(QM_GPIO_0, &cfg);

Why the GPIO2 can't assign to output?

Please help check this problem. Thanks~

Below is my SPI and GPIO setting.

// SPI setting //

qm_pmux_select(QM_PIN_ID_42, QM_PMUX_FN_1); /* SPI1_M SCK */

qm_pmux_select(QM_PIN_ID_43, QM_PMUX_FN_1); /* SPI1_M MISO */

qm_pmux_select(QM_PIN_ID_44, QM_PMUX_FN_1); /* SPI1_M MOSI */

qm_pmux_select(QM_PIN_ID_45, QM_PMUX_FN_1); /* SPI1_M SS0 */

qm_pmux_select(QM_PIN_ID_46, QM_PMUX_FN_1); /* SPI1_M SS1 */

qm_pmux_select(QM_PIN_ID_47, QM_PMUX_FN_1); /* SPI1_M SS2 */

qm_pmux_select(QM_PIN_ID_48, QM_PMUX_FN_1); /* SPI1_M SS3 */

qm_pmux_input_en(QM_PIN_ID_43, true);

/* Initialise SPI configuration */

cfg.frame_size = QM_SPI_FRAME_SIZE_16_BIT;

cfg.transfer_mode = QM_SPI_TMOD_TX_RX;

cfg.bus_mode = QM_SPI_BMODE;

cfg.clk_divider = SPI_CLOCK_DIV;

int ret __attribute__((unused));

ret = qm_spi_set_config(QM_SPI_MST_1, &cfg);

QM_ASSERT(0 == ret);

ret = qm_spi_slave_select(QM_SPI_MST_1, QM_SPI_SS_0);

QM_ASSERT(0 == ret);

// GPIO setting //

qm_gpio_port_config_t cfg;

/* Request IRQ and write GPIO port config. */

//cfg.direction = BIT(2)|BIT(4)|BIT(5)|BIT(6)|BIT(7);

cfg.direction = BIT(4)|BIT(5)|BIT(6)|BIT(7);

cfg.int_en = BIT(QM_PIN_ID_3); /* Interrupt enabled. */

cfg.int_type = BIT(QM_PIN_ID_3); /* Edge sensitive interrupt. */

cfg.int_polarity = ~BIT(QM_PIN_ID_3); /* Falling edge. */

cfg.int_debounce = BIT(QM_PIN_ID_3); /* Debounce enabled. */

cfg.int_bothedge = 0x0; /* Both edge disabled. */

cfg.callback = NULL;

cfg.callback_data = NULL;

QM_IR_UNMASK_INT(QM_IRQ_GPIO_0_INT);

QM_IRQ_REQUEST(QM_IRQ_GPIO_0_INT, qm_gpio_0_isr);

/* enable pullup on interrupt pin. */

qm_pmux_pullup_en(QM_PIN_ID_3, true);

qm_gpio_set_config(QM_GPIO_0, &cfg);

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2 Replies
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I have tried to reproduce your issue here - but I can't.

Can you try explicitly muxing out QM_PIN_ID_2 just to be sure it's set to the correct function ....

qm_pmux_select(QM_PIN_ID_2, QM_PMUX_FN_0);

- Michelle

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Beginner
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Hi Michelle :

The GPIO2 pin connected to my LoRa module RESET pin, and RESET pin is pull high.

So, I try to add below setting befor configuration GPIO.

qm_pmux_select(QM_PIN_ID_2, QM_PMUX_FN_0);

qm_gpio_set_pin(QM_GPIO_0, QM_PIN_ID_2);

qm_pmux_pullup_en(QM_PIN_ID_2, true);

Then testing again, SPI-1 interface read/write workable.

Thanks~

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