I am working QUARK SOC.Below is my clarification on Power sequencing.
I have observed SOC POWER Sequence mismatch between PDG and Ref Design :
Below are the reference document names and attached block diagrams for your reference.
PDG : quark-x1000-platform-design-guide_003.pdf Page 98 and
Ref design: 545112_KipsBay_FabD_Schematics_Rev1_0.pdf
I will provide you one example where I see mismatch,
TPS652510 is generating 3 outputs which are V3P3_S5,V1P0_S5 and V1P5_S5 In PDG where as in ref-design V3P3_S5,V1P0_S0 and V1P5_S5. I see major mismatch in V1P0_S5 & V1P0_S0.And I see V1P0_S5 in PDG block diagram it is interfaces to SOC but not shown where it is getting connected on SOC.
Could you please check and let me know which one to follow PDG or reference design.
Here are the links...
PDG Link :It is version 3
Reference design linkSchematic and Layout Files:Intel® Quark™ SoC X1000 Customer Reference Board: Schematics5451121Mar 2014Schematics: design diagrams of customer reference board. (v.1, Mar. 2014)
Please check and let me know which one to refer.
Thank you for your patience.
According to the note just above Figure 47 of the Platform Design Guide:
"Figure 47 is only a block diagram and should not be treated as schematic. Refer to the Intel ® Quark SoC X1000 reference design schematics for the full implementation".
Refer to the Intel® Quark™ SoC X1000 Customer Reference Board: Schematics.