We have created custom board with Quark X1000 reference design files, 60% of our boards are not getting through the power sequence of Quark, It enables the S3_3V3_EN(after S5) but do not provide enable signal for further voltages.
Also the reset line raises up to 400mV & comes down to 0V.
I could not find the reason why Quark is not enabling the other supply by providing further enable signals, please provide me the reasons or documents which have further details on why it will stop the power sequence.
40% PCB's are working while 60 % are not working with same PCB revision & components.
I have already checked the PMIC but it is working fine & providing 3.3V, 1.5V & 1V at output in all our pcb.
What can be the possible reasons for not completing power sequence?
Please provide details asap.
Thank you for contacting us and attaching the picture. We'll try to help you with this case.
I took a look at the picture you attached. You mention that S3_3V3_EN doesn't provide enable signals but after it goes from LOW to HIGH, all the other signals in S3 rail are later switched to HIGH and remain that way. The only signal I could see that goes from HIGH to LOW is PWR_BTN_B. I noticed you put a note on the picture about the power button and this signal but it's difficult to read because the text covers that note. Could you clarify what's in the note?
According to the Quark, datasheet S3_3V3_EN is active HIGH and about PWR_BTN_B
"Power Button: Two modes of operation. 1. A power button press is required to complete cold boot. Active LOW. 2. The button is tied low, results in an automated start at power on."
I'd suggest you to check Chapter 9 of the Quark Datasheet. It's a dedicated chapter to Power up sequence, you may find useful information here http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html .
We'll be waiting for your response.
Thank you for the prompt response.
I have used the diagram of the Quark datasheet for reference :
We are getting below pin states :
Power_BTN : low (as expected,tied to gnd via 10K)
VCC3P3_S5 : 3.3V
VCC1P5_S5 : 1.5V
VCC1P0_S5 : 1.0V
X1000Vout-OVOUT_1P8_S5 : 1.8V
X1000Input-S5_PGOOD : 3.3v
X1000Output-S3_3V3_EN : 3.3v
but the X1000 Output-S3_1V5_EN & following sequence is disabled.
In a nutshell the Quark doesn't enable the EN signal for the S3 domain (1.5V & 1.0V) & S0 domain (3.3V,1.5V & 1.0V).
Please let me know the possible reasons for S3_1V5_En & other signals being not enabled for Quark.
Thank you for sending us the pin states and sending the signals diagram. I reviewed the pin states you sent and those seem to be correct. I also looked at the signal diagram and you're right, after comparing your signals to the ones in Figure 21 there's a difference. I noticed because of the note about S0_1P0_PG and S0_1V5_EN.
I've some questions about your general setup-you say that 60% of your boards are not working while 40% are. Are you testing these boards separately or are the boards somehow connected together or sharing the power supply? Have you set any other configuration or external circuitry?
There's more information about the power up sequence here http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-platform-design-guide.htm... http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-platform-design-guide.htm... Section 14
We'll be waiting for your response.
Thank you for attaching the Reflux diagram. I compared the diagram against the one in the PDG. The only time range that doesn't fit the values on the PDG is the peak time, which should last from 10 to 30s and in your case is 42s. We'll take this and investigate further on your case and look for reasons why the your design is not working as it should. We'll contact you back as soon as we have more information.
We're still working on your case. We've sent you some information through a private message. Please check your inbox. We'll be waiting for your response.
Thank you for reference of the document sergio.
I have gone through the section 14,15 of PDG & Datasheet section 9.
But i could not find out the reason for the Quark for not pulling up the Enable signal of S3 & S0 domain(the board which are not enabling the power sequence also have Reset signal pulled low(it tries to pull up the reset signal but eventually it falls down to 0V)).
We are testing all the boards individually & have no interconnections.
Please find below the profile used ( i have referred to the reflow profile provided in Platform design guide Appendix B)
40% assembled pcb have issues with lspi flash communication(A3 works for few section of coding while A4 & A5 do not respond to code after one cycle.Please find below the details on same.
What are the possible reason for the Quark to stop communication with the SPI flash connected on Lspi?
I request to provide me the support asap on the issues because 40% of boards have power sequencing ok but wont be running with the program & 40% of the PCB have issues with the power sequence.
Please tell me the probable reasons for below two issues asap:
->LSPI flash not able to communicate( have power sequencing working).
->The reset signal being pulled down(power sequence not enabled for S3 & S0 domain).