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FGold
New Contributor II
983 Views

SPI Clock appears to be on a different pin then the documentation

the SPI0 Clock (SPICLKB) appears to be located on J13.25, which is labelled SPP0FS3: GPIO SPI?

0 Kudos
7 Replies
idata
Community Manager
23 Views

Hello floydg,

 

 

Thanks for reaching out!

 

 

I'm afraid I don't understand your doubt. Could you please explain us the issue?

 

 

Anyway, I checked the following document: http://www.intel.com/content/www/us/en/support/boards-and-kits/intel-joule-kits/000022494.html and as you mentioned, the pin 25 of J13 is labeled SPI_0_CLK.

 

 

You also mention that you are noticing a mismatch between the documentation and the place where SPI_0_CLK actually is. How did you notice this? On which document did you notice this?

 

 

If I'm not mistaken, the document I shared above is congruent with what you mention, right?

 

 

I hope this information helps you, if this is not the case, please let me know and I would be more than glad to help.

 

Pedro M.
FGold
New Contributor II
23 Views

Hi,

according to the "Golden Intel link" (MRAA 1.51 Intel Joule):

https://iotdk.intel.com/docs/master/mraa/grossetete.html mraa: Intel Joule

pin 65 states SPP0FS3 GPIO SPI. Pin 65 is on J13: 65-40 = J13.25

The document contradicts itself by also stating:

SPI

Two SPI buses are available, with one chipselect each. Pins listed are MRAA numbered pins. Other chip selects are available if enabled in BIOS/EEPROM but cannot be enabled as BIOS options. You will need the spidev kernel module loaded, Ostro-XT does this by default.

Bus 0 (32765) MOSI = 2 MISO = 4 CS = 6 CLK = 10

Bus 1 (32766) MOSI = 67 MISO = 69 CS0 = 59 CS1 = 61 CLK = 65

Also

> mraa-gpio list

64 SPICLKB: GPIO

65 SPP0FS3: GPIO SPI

66 SPICLKA: GPIO

67 SPP0TX: GPIO SPI

If I recall correctly, when testing this SPI interface, the logic analyzer displayed the SPI clock on Pin 65

The link you provided above does appear to show the correct pin assignment (Pin 25 SPI_0_CLK):

Note:

root@intel-corei7-64:~# mraa-gpio version

Version v1.5.1-24-g2ea6810 on Intel GT Tuchuck

root@intel-corei7-64:~# uname -ra

Linux intel-corei7-64 4.4.36-yocto-standard # 1 SMP PREEMPT Fri Dec 16 16:15:48 U

TC 2016 x86_64 GNU/Linux

root@intel-corei7-64:~#

idata
Community Manager
23 Views

Hi floydg,

I see what you are referring to. I will report this to the appropriate team, hopefully it can be corrected soon. In the meantime I suggest you to refer to the document I shared above: http://www.intel.com/content/www/us/en/support/boards-and-kits/intel-joule-kits/000022494.html http://www.intel.com/content/www/us/en/support/boards-and-kits/intel-joule-kits/000022494.html.

Pedro M.

FGold
New Contributor II
23 Views

Pedro,

this is a disturbing and an unacceptable response!

And may result in thousands of dollars wasted due to a misrepresentation.

The community has been designing systems with schematics based on the information from:

according to the "Golden Intel link" (MRAA 1.51 Intel Joule):

https://iotdk.intel.com/docs/master/mraa/grossetete.html mraa: Intel Joule

and not from the relatively newer document (1/24/2017):

Intel® Joule™ Expansion Board Breakout Definition for Linux*

Last Reviewed: 24-Jan-2017

Article ID: 000022494

http://www.intel.com/content/www/us/en/support/boards-and-kits/intel-joule-kits/000022494.html http://www.intel.com/content/www/us/en/support/boards-and-kits/intel-joule-kits/000022494.html.

***************************************************

THIS NEEDS TO BE ADDRESSED ASAP!!!!!!

***************************************************

From: intel-joule-expansion-hardware-guide.pdf

Page21: Eight dedicated GPIO signals, and seven user programmable GPIO signals

page 24:

GPIO Pins J13.16, J13.18, J13.20

page 25:

GPIO Pins J13.34, J13.36, J13.38, J13.40

idata
Community Manager
23 Views

I understand what you mean. I will ask the team in charge to prioritize this issue. We appreciate your patience and apologize for any inconvenience this might cause.

 

 

Pedro M.
FGold
New Contributor II
23 Views

Pedro,

hope all is well.

Any status?

idata
Community Manager
23 Views

Hello floydg,

I apologize for the delay in my response, we have an update for this case.

The pins you are looking at are, in fact, the same (SSP0FS3 = SPI_0_CLK). The MRAA naming convention comes from the software team who found repeating signal names for different signals when creating the table. While some of the MRAA signal names are not clearly representative of the pin attributes, the pins are as specified in: http://www.intel.com/content/www/us/en/support/boards-and-kits/intel-joule-kits/000022494.html http://www.intel.com/content/www/us/en/support/boards-and-kits/intel-joule-kits/000022494.html

We are aware of the discrepancies on certain documents and we are currently working to close the gap in documentation.

 

Pedro M.