I am having trouble getting SPI Master to operate.
I was planning to handle the SS manually in software - as it has some additional functionality in our system.
After many hours of not being able to get the SPI to transmit I tried enabling a SS in the SER register and suddenly it came to life. Can you confirm that this is an operating requirement? It seemed to work even if I don't use pmux_sel to bring the line out.
In case I decide to use the SS output form the SPI peripheral can anyone advise when the SS is returned high in TXRX mode. Is it after each byte or only when FIFO is empty.
Any update form the data sheet with these kinds of issues addressed?
The SS, or SPI_M_SS[3:0] is the Master SPI Slave Select. The SPI_M_SS should be enabled so that the SPI can work properly.
The D2000 datasheet also mentions in section 15.2 "FIFO mode support with 8B deep TX and RX FIFO's". You can see more information on the various SPI functions and how they're used in IntelSWTools/ISSM_2016.0.027/firmware/bsp/1.0/doc/html/group__groupSPI.html
As for the documentation, if there are updates in the datasheet, an announcement will be made in the community.
I am wondering if we are looking at the same documents. The data sheet I have says "Control of up to 4 slave selects". I do not find any reference to it being mandatory to have at least 1 slave select. SPI is often done without slave select. And when it is used, it is used differently - some times between each byte and some times between frames and sometimes not at all. It is not uncommon for CS on the slave to be grounded.
I checked IntelSWTools/ISSM_2016.0.027/firmware/bsp/1.0/doc/html/group__groupSPI.html
While it describes a function
qm_rc_t qm_spi_slave_select (const qm_spi_t spi, const qm_spi_slave_select_t ss)
I could not find any overarching documentation on what functions should be called or any where that says its calling is mandatory.
I still can not find anything that describes the Slave Select operation between bytes of frames
From your explanation it would appear that the operation for the SER register does not follow the description in the Datasheet(the latest datasheet has the same explanation). We will need to test this and raise a bug if required.
SS should be retuned high only when the FIFO is empty.
However we currently have a bug where the SPI slave select de-asserts after a small number of bytes are transferred Workaround is to use a GPIO pin
we are working on this currently..
In addition to Michelle's explanation:
Q1: For starting a transfer, this controller demands at least one slave select line (SS) to be enabled, although it is not necessary to mux the line out. Thus, a call to "qm_spi_slave_select()" (this function may vary depending on the BSP version you are using, you will find it in qm_spi.h in the latest release) with one of the four SS valid lines is mandatory. This is true even if the native slave select line is not used (i.e. when a GPIO is used to drive the SS signal manually).
Q2: No additional comments.
Q3: We are currently reviewing the datasheet to add more clarity on the SPI section. What version of QMSI BSP are you working with?