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JJare1
Novice
2,167 Views

Slow clock rate for SPI peripheral on J12 in Linux

I've noticed that the SPI peripheral available on J12 is significantly slower than the one available on the J13 header.

Taking a look at the /sys/kernel clocking information reveals that the clock signal that feeds SPI port on J12 pins (2,4,6,8,10) is set to 1 MHz.

cat /sys/kernel/debug/clk/pxa2xx-spi.13-div/clk_rate

1000000

./spidev_test -D /dev/spidev32766.0 -s25000000 -l

On the J12 SPI port, It will not go faster than 1MHz, because the peripheral input clock is at 1MHz.

The other SPI port on J13 (19, 21, 23, 25, 27, 29) is fed by a 50 MHz clock

cat /sys/kernel/debug/clk/pxa2xx-spi.14-div/clk_rate

50000000

./spidev_test -D /dev/spidev32766.0 -s25000000 -l

On J13's SPI port, I was able to get the spidev_text.c program to correctly run up to 25MHz, which is maximum clock rate listed in the datasheet.

Any suggestions on how to increase the input clock that feeds the SPI peripheral accessible on J12?

Is there a particular reason this clock is set to 1 MHz? Perhaps another device on the bus using one of the other chip selects?

-Jam

13 Replies
JJare1
Novice
134 Views

copy and paste error in post above. the SPI port on J12 is /dev/spidev32765.0

./spidev_test -D /dev/spidev32766.0 -s25000000 -l

should read

./spidev_test -D /dev/spidev32765.0 -s25000000 -l

when using the SPI on J12

idata
Community Manager
134 Views

Hello jam531,

 

 

Thank you for interest in the Intel® Joule™ Products.

 

 

I'll be needing more time to come up with information that you may find relevant. As soon as I find something that may help solve your issue, I'll contact you through this post.

 

 

Thank you for your patience.

 

 

Regards,

 

Andres
JJare1
Novice
134 Views

Hi Andres,

Thanks for taking a look at this for me. My Linux kernel knowledge and experience is limited, but I was not able to effectively trace down these settings while poking around the kernel source, thus I have a couple of questions.

1) Is this something that is configured by a boot-loader or piece of software that initializes the system prior to the kernel being up and running (IE: like certain memory timing settings)?

2) How is peripheral information passed to the kernel on this platform? Is there a device tree or equivalent structure?

Ultimately I'm trying to have both user accessible SPI peripherals on the development kit clock out at 25MHz and use DMA during transfers.

-Jam

idata
Community Manager
134 Views

Hello Jam,

 

 

I did a couple of tests and came up with the same results for the following commands:

 

cat /sys/kernel/debug/clk/pxa2xx-spi.13-div/clk_rate

 

1000000

 

 

cat /sys/kernel/debug/clk/pxa2xx-spi.14-div/clk_rate

 

50000000

 

 

But I also performed tests to check the SPI port frequency, and came with some interesting results:

 

• The max frequency in J12 is the same as yours, 1 MHz

 

• The max frequency in J13 is 12.5 MHz

 

 

I'm aware that the datasheet presents the max frequency as 25 MHz, so I'm also interested in understanding this behavior, and performing more tests.

 

 

Could you please share the procedure you used to change the frequency of J13, and a link to the spidev_test.c code that you used in order for me to replicate your tests?

 

 

I'll be waiting for your response.

 

 

Regards,

 

Andres
JJare1
Novice
134 Views

Hi Andres,

Thank you for looking into to this for me. The spidev_test.c program is the generic one in ostro-os-xt/build/tmp-glibc/work-shared/intel-corei7-64/kernel-source/Documentation/spi/spidev_test.c. For the source to appear you may need to execute:

cd ostro-os-xt/

source ostro-init-build-env

bitbake linux-yocto

bitbake linux-yocto -c menuconfig

bitbake -f linux-yocto -c compile

I don't think the actual kernel source code will be be in those directories by default. Once the test program is compiled, move it over to the board and execute the commands:

./spidev_test -D /dev/spidev32765.0 -s25000000 -l

./spidev_test -D /dev/spidev32766.0 -s25000000 -l

I've noticed that if you want to be able to run at 25MHz from a program that uses MRAA library code you have to do one of two things first:

Option 1:

run './spidev_test -D /dev/spidev32765.0 -s25000000 -l' before running a program that uses the MRAA library.

Option 2:

modify the file ostro-os-xt/build/tmp-glibc/work-shared/intel-corei7-64/kernel-source/init/main.c file

and update the .max_speed_hz fields for all of the SPI ports

I created a patch for you which I'll paste below:

diff -Naur a/init/main.c b/init/main.c

--- a/init/main.c 2017-01-27 21:11:01.013743478 -0500

+++ b/init/main.c 2017-01-27 21:13:20.117743667 -0500

@@ -934,37 +934,37 @@

.modalias = "spidev",

.bus_num = 32766,

.chip_select = 0,

- .max_speed_hz = 12000000,

+ .max_speed_hz = 25000000,

},

{

.modalias = "spidev",

.bus_num = 32766,

.chip_select = 1,

- .max_speed_hz = 12000000,

+ .max_speed_hz = 25000000,

},

{

.modalias = "spidev",

.bus_num = 32765,

.chip_select = 0,

- .max_speed_hz = 12000000,

+ .max_speed_hz = 25000000,

},

{

.modalias = "spidev",

.bus_num = 32765,

.chip_select = 1,

- .max_speed_hz = 12000000,

+ .max_speed_hz = 25000000,

},

{

.modalias = "spidev",

.bus_num = 32764,

.chip_select = 0,

- .max_speed_hz = 12000000,

+ .max_speed_hz = 25000000,

},

{

.modalias = "spidev",

.bus_num = 32764,

.chip_select = 1,

- .max_speed_hz = 12000000,

+ .max_speed_hz = 25000000,

},

};

Then recompile the kernel and move it to the Joule. After that kernel change, programs that use the MRAA libraries can use the 25MHz speed. Although the clock rate can be 25MHz, it looks like the driver (as it currently stands) defaults to polled I/O (PIO) mode, which is significantly slower than the DMA mode. This is causing large pauses between SPI transfers, which significantly slows down the SPI communications.

-Jam

idata
Community Manager
134 Views

Hello Jam,

 

 

You are welcome, and thank you for the information provided.

 

 

I'll be needing more time to analyze the code, the steps provided and perform the corresponding tests. I'll contact you through this post as soon as I find relevant information.

 

 

Thank you for your patience.

 

 

Regards,

 

Andres
idata
Community Manager
134 Views

Hello Jam,

 

 

I performed the tests and even thought I still need to further analyze the results, I wanted to share them with you.

 

 

I used the same spidev_test.c program, and after compilation, I ran the following commands:

 

./spidev_test -D /dev/spidev32765.0 -s25000000 –l

 

./spidev_test -D /dev/spidev32766.0 -s25000000 –l

 

 

The relevant results are the following:

 

SPI port on J12

 

./spidev_test -D /dev/spidev32765.0 -s25000000 –l

 

spi mode: 0x20

 

bits per word: 8

 

max speed: 25000000 Hz (25000 KHz)

 

 

SPI port on J13

 

./spidev_test -D /dev/spidev32766.0 -s25000000 –l

 

spi mode: 0x20

 

bits per word: 8

 

max speed: 25000000 Hz (25000 KHz)

 

 

The results are not compatible with what you experienced, since you told me you got 1 MHz from J12. Also they are not compatible with my other test (where I got 1 MHz for J12, and 12.5 MHz for J13).

 

 

Obviously, further analysis is being done, and I hope to come with relevant information soon.

 

 

Thank you for your patience.

 

 

Regards,

 

Andres V.
JJare1
Novice
134 Views

Hi Andres,

Just to confirm; were the speeds listed in your last post verified with a logic analyzer or oscilloscope or self reported by the software? The 1MHz, and 25MHz clock rates in my earlier posts were verified with a Logic Analyzer.

Sincerely,

-Jam

idata
Community Manager
134 Views

Hello Jam,

I performed new tests using a Logic Analyzer, and even thought I still need to further analyze the results, I wanted to share them with you.

Again, I used the same spidev_test.c program, and after compilation, I ran the following commands:

 

./spidev_test -D /dev/spidev32765.0 -s25000000 –l

 

./spidev_test -D /dev/spidev32766.0 -s25000000 –l

The relevant results are the following:

 

SPI port on J12

 

./spidev_test -D /dev/spidev32765.0 -s25000000 –l

 

spi mode: 0x20

 

bits per word: 8

 

max speed: 25000000 Hz (25000 KHz)

 

Logic analyzer max frequency: 62.42 kHz

SPI port on J13

 

./spidev_test -D /dev/spidev32766.0 -s25000000 –l

 

spi mode: 0x20

 

bits per word: 8

 

max speed: 25000000 Hz (25000 KHz)

 

No readings for any value, screen and logic analyzer show the following:

 

RX | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................................

The results are not compatible with what you experienced, since you told me you got 1 MHz from J12. Also they are not compatible with my "mraa test" (where I got 1 MHz for J12, and 12.5 MHz for J13).

Obviously, further analysis is being done, and I hope to come up with relevant information soon.

Thank you for your patience.

Regards,

 

Andres V.

 

idata
Community Manager
134 Views

Hello Jam,

 

 

Sorry for the late reply.

 

 

After doing some research, there is some information that you may find useful:

 

• The SPI level translators are limited to reach a theoretical value between 4 MHz and 7 MHz. The Joule compute module itself is capable of reaching faster SPI speeds, but the expansion board limits the speed to that of the level translation devices.

 

 

• The software limits the clock speed to 1 MHz to assure a proper SPI signal according to the level translator devices present in the expansion board.

 

 

• There are 3rd party expansion boards available for the Joule compute module that provide different level translation solutions, and one of these might better meet your development needs.

 

 

I hope you find the previous information useful.

 

 

If you have any other question, don't hesitate to contact us.

 

 

Regards,

 

Andres V.
JJare1
Novice
134 Views

Hi Andres,

Thank you for your response. Unless the lines are loaded with more capacitance than I expect, the buffers on the development board should be capable of the full speed. I seem to recall seeing the 25MHz working on at least one of the ports and both SPI port signals use the same type of level translator.

I had to go with another SOM solution for my current projects, but it may be helpful to post the steps and changes needed to adjust the clock rates in software for others looking to go down this path in the future.

-Jam

idata
Community Manager
134 Views

Hello Jam,

 

 

I'm sorry to hear that you had to search for another solution due to the lack of documentation.

 

 

I'll inform the proper team about your request, and ask for a step-by-step guide on how to change the clock rates of the Joule Compute Module.

 

 

Thank you for your patience and for sharing your experience with the community, we really appreciate it.

 

 

Regards,

 

Andres
SZamb1
Novice
134 Views

Hello,

we also experienced problems with SPI, and in the meanwhile found out more about this issue.

As jam513 was suspecting, it has nothing to do with the level translators on the carrier board, which are these:

http://www.ti.com/lit/ds/symlink/lsf0108.pdf http://www.ti.com/lit/ds/symlink/lsf0108.pdf

and from the specs it's specified that they support "Up to 100 MHz Up Translation and Greater Than 100 MHz Down Translation at ≤ 30pF Cap Load and Up To 40 MHz Up/Down Translation at 50 pF Cap Load".

By looking at ACPI disassembly it seems that there are a bunch of SPI-related items, so probably the issue can be fixed with a BIOS update.

Cheers,

 

Stefano
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