For the last several weeks; I've been working on a custom PCB project for my Intel Edison. Some friends suggested it might be of interest here; and I'd value any constructive feedback toward it's design. The PCB design incorporates the Intel Edison connector to interface with a 4port USB hub. Attached to that hub are the following ASICs:
The goals of the project is to enable expanded storage thru the SSD and temporary Swap space for the Linux and WindowsXP OSes on the Intel Edison. The PCB is a 4layer implementation which implements a modified Sparkfun Edison block form factor. Current PCB measures at 4.5"x2.15". Additionally I've included the Intel reference design for the LIPO battery charger to provide a limited UPS-type capability incase of small power outages.
More details are available at my personal blog at:
http://pinball-mods.com/blogs/?p=580 Intel Edison: USB Storage Sled | Zitt's Blog
I'm attaching the prototype Schematics here for peer review and comments... feel free to send me comments/questions here or at the blog. I'm taking constructive feedback thru the end of week; at which point I'm probably going to commit the design to OSHPark's PCB service. The Schematics are currently ALL RIGHTS RESERVED except where noted. Same for the Layout. At the moment; I plan to convert the project to TAPR/NCL once I've gotten the project verified as working.
It's been a while; but I have been debugging the design as time permits. Upon initial assembly using a hot skillet reflow in the garage; I had some issues with the Edison high-density connectors. After getting that sorted; the USB hub and PATA chip identified themselves to my netbook. putting a USB memory stick on the DD interface of the hub showed that I could read/write the USB bus.
The USB hub is seen by the Edison in "host mode" and by J16 (host computer) in device mode. I can download Arduino sketches via J16 when in device mode.
Initial debug showed several issues:
I'm going to try and find the right package for U36 and more importantly figure out how to dead-bug rework a EEPROM to the AT2LP to see if I can get that interface online in the near future.
The other thing which needs to be done; but is likely beyond my home workbench capabilities is to do a USB dataeye analysis to see if there is any margin in the design.
After attaching a I2C eeprom to the AT2LP; the PATA interface came up.
mSATA interface is working fine.
Basically; all of the interfaces are working as expected including the USB muxes in the design.
Been working on FabB of the design; correcting minor issues found. Really all I need to do is add a I2C eeprom to the PATA controller and correct the I2C eeprom on SATA. No sense of urgency here as there seems to be little interest in this design publically.