I've noticed that in section 7.2.3 (J7 connector interface signals) on the datasheet, some pins and signal descriptions are missing. Was this intentional or an accidental oversight?
P.S. In the Intel Joule Expansion Board Schematics the mating connector (J3 on schematic) has these signals labelled.
Thank you for reporting this. I'm looking at this datasheet http://www.intel.com/content/www/us/en/support/boards-and-kits/000022327.html http://www.intel.com/content/www/us/en/support/boards-and-kits/000022327.html from September 2016. Could you please mention specifically which pins and signal descriptions are missing?
I'll be waiting for your response.
We already have some updates on this case, thank you for your patience.
J7 pins 48 and 91 should be connected to GND. These are for signal integrity of USB signals.
For remainder pins, the Joule Datasheet may be updated in a future version. The timing of an update is subject to change without notice, so we encourage you to keep checking the Communities and the available documentation.
In terms of the pin-out, I think I am alright for now. I did have a question about the Joule documentation in general. Will detailed information such as a processor reference manual with all of the peripheral register mappings be made available? Is there documentation that outlines timing constraints such as set-up times, hold times, or anything that outlines timing diagrams for the peripherals accessible on the headers?
We want to provide as much information about the Joule documentation as we can but, at this point, we don't have the details of what will be included in future revisions of the datasheet. We're working to update some documents and creating new ones, but the contents of each section have not been disclosed yet. Thank you for your understanding.