As far I know, when a processor wants to store a value to some memory location, the value is stored to the processor's cache, and then populated to actual RAM. This way the value is also automatically cached for reading.
My question is: is the value stored only to L1 cache, or is it also stored to L2 and L3 caches?
In other words: will the value be automatically cached for reading also for other cores (who share L2 or L3 cache)?
Both exclusive and inclusive (as well as mainly exclusive) caches are used:
You must consult documentation on your particular processor model.
Most current architectures store updates first in a cache line buffer, called fill buffer on Intel CPUs since Woodcrest. Varying strategies are used to update cache when an event requires it, such as a read.
Going backwards in time, and simplifying to an outrageous degree:
For Intel Core I7 architecture, L3 is not updated until the data are accessed by a core other than the one which modified them. L1 and L2 are exclusive, so the update will appear on only one of them, on only one core, until accessed by another core. Cache coherency hardware takes care of L3 update automatically.
Core 2 architecture updated L1 and L2 (shared) immediately.
NetBurst architecture updated L2 (shared) and invalidated L1.
Non-temporal store invalidates the entire cache line at all levels.