I am working on inclusion property in multilevel cache systems. Can anyone of you tell me if Intel ensures inclusion property at every level of cache in their multicore architecture?
What does intel processors use for ensuring cache coherency? Snooping or invalidation techniques? I appreciate any type of help on these..
Robert Said, "Any implementation insights? The last level cache is inclusive: if a cache line lives in L1 or L2 on one of the cores, it will also have a place in the L3and yes, it helps to reduce snoop traffic. But not eliminate it--still need snoops from L3 if you've got multiple sockets. But, we are getting far afield from the topic of this thread. If you want to continue with these questions,I think you should start a thread with a more appropriate title."
Yes, I understand what inclusion means. I wanted it's actual implementation details. In the sense - do they use an inclusion bit too keep track of all the cache lines existing in lower level caches? Or is there some other efficient technique?
Great! L3 snoops to see if some other processor writes to the memory. Makes sense. By any chance, can a I/O write to a memory location which can be cacheable?