Netburst and Core

[folgora]

First i am sorry if i am in the wrong dorum section.
But i need to do a architecture comparison between Netburst and Core architectures.
But i dont know and cant find any relevant data for that matter.
So if anybody could help me what i should put in it, that would be very helpful.

[TimP]

Quoting - folgora

First i am sorry if i am in the wrong dorum section.
But i need to do a architecture comparison between Netburst and Core architectures.
But i dont know and cant find any relevant data for that matter.
So if anybody could help me what i should put in it, that would be very helpful.

This forum article
http://software.intel.com/en-us/forums/showthread.php?t=63138
gives you the site for the most authoritative reference. So, you can see your topic is touched on by several forum sections.
In my opinion, you will need to do quite a bit of reading between the lines.
NetBurst emphasized support of the highest possible clock speeds, sometimes at the expense of useful performance and power consumption, while Intel's trumpeted "right hand turn" to Core architecture increased the instruction issue width (more instructions per clock, shorter pipelines) and began to emphasize performance per watt.
The HyperThread feature was removed from Core (to be revived, with some improvements, in Core i7).
Dual core mobile and quad core desktop and server CPUs were first introduced in Core.
Some of the more serious bottlenecks (besides instruction issue width) were alleviated in the transition from NetBurst to Core.
The Core architecture Fill Buffers fill a function equivalent to the NetBurst Write Combine Buffers. 32-bit NetBurst had 6 WCBs, increased to 8 in 64-bit NetBurst, while Core 2 has 10 fill buffers. Core Fill buffers write out to L1 cache, reducing the latency of buffer flushes followed by data reads, where NetBurst WCBs write out to L2. Some of this stuff was secret up past CPU introduction, so is difficult to find in docs.
The original NetBurst WCB scheme supported efficient operation up to but not beyond 4 data write streams per loop (2 under HyperThreading), which had visible implications for software optimization, particularly with the original memory systems. Better advantage of Core 2 may be taken by using up to 8 write streams or sometimes more.
Core 2 introduced 2 levels of Data Translation Lookaside Buffer, with a small TLB for L1 and a 256 entry TLB for L2 (still not large, considering the small page size of 4KB, which was retained). The high performance penalty of in-cache L2 DTLB miss on NetBurst was reduced to a more competitive value in Core 2, but with the addition of an L1 DTLB miss penalty which is observed in some situations.
A minor instruction set addition came with the initial transition from 64-bit NetBurst SSE3 "Prescott/Nocona" to Core 2 SSSE3 "Merom." Compilers initially attempted to exaggerate the difference by reserving some optimizations for SSSE3. That didn't work out well, as applications had to continue to support SSE2 and SSE3, SSE3 became an industry standard, and the number of minor instruction set variations has introduced serious software QA implications. SSE4 introduced some new instructions in the last Core 2 architecture (Penryn). Gnu and Intel compilers make different choices about which SSE4 instructions they find useful.
All this is history, as the Core i7 and its server counterpart have changed the cache hierarchy stuff significantly, while retaining excellent compatibility with software optimized for Core 2. Core i7 introduced another almost insignificant instruction set augmentation.
Evidently, my interpretation of important changes (from HPC application tuning point of view) is quite different from the marketers' interpretation, and from the emphasis in the early architecture manuals. You will need to define your viewpoint and discuss how it requires you to interpret the importance of the various features. If you agree with my interpretation, you still have your work cut out to find the basis in authoritative and not so authoritative references.

[gaston-hillar]

Quoting - folgora

First i am sorry if i am in the wrong dorum section.
But i need to do a architecture comparison between Netburst and Core architectures.
But i dont know and cant find any relevant data for that matter.
So if anybody could help me what i should put in it, that would be very helpful.

Hi folgora,

You are going to compare very different micro-architectures. What kind of application are you going to use in order to make the comparison? Are you going to run benchmarks or do you want to make a theorical comparison?

[srimks]

Quoting - folgora

First i am sorry if i am in the wrong dorum section.
But i need to do a architecture comparison between Netburst and Core architectures.
But i dont know and cant find any relevant data for that matter.
So if anybody could help me what i should put in it, that would be very helpful.

Please refer Chapter 2 of "Intel 64 & IA-32 Architectures, Optimization Reference Manual" document.

~BR