Some basic questions :
I) In the Xeon 3.06 w/1MB L3, the L3 - L2 relation is :
(a) mostly exclusive
(b) mostly inclusive
(c) too complex to be described
(d) a trade secret
II) If we compare the L3 cache behavior of the Xeons 3.06 w/1MB L3 and the latest Xeons MP with 1MB L3, we can say it is :
(a) 100% the same
(b) mostly the same with small differences
(c) completely different
(d) this information isn't disclosed
Let's not forget that 1) there are tremendous benefit in having a on-die level 3 cache. 2)Both Level 3 Cache designs are full speed, 8-way associative with ECC capability.
Thanks for those answers ISN Admin.. I need a bit more clarification.
Is L2 inclusive of L1 as well in the latest multicore architectures by intel, say nehalem?
Further, what do they do to solve the cache coherence problem? Invalidation or snooping?