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Message Edited by tim18 on 10-28-2005 06:46 PM
From what I can interpret, HT suffers from a cache that was designed for a single (virtual) processor. If more effort is put into the cache design to eliminate aliasing of addresses then most of the adverse cache interaction would be eliminated (but there will undoubtably be a second most adverse cache interaction). Other than for dual cores or multi-cores, or multiple chips the cache interaction is likely to remain (why put the effort into fixing an old design).
This brings me to the question that someone might be able to answer. On a single core with HT can the cache-ing be disabled for one of the virtual processors? Let one thread run slower (but not trash the other thread's cache).
But unfortunately the FORTRAN allocate as well as the C/C++ do not permit entering a hint at perfered alignment restrictions. e.g. if your application determines it is on a single core HT capable system with 4MB aliasing then there is no means to have the allocate specify a preference to obtain memory from a particular 2MB alignedportion of memory. The C++ programmer has the means to correct for this by replacing the new handler but the Fortran programmer does not have this functionality.