I have discovered several errors pertaining to DDR4 SDRAM configuration posted in table form within the published Technical Product Specs of several NUC series supporting DDR4 SODIMM memory. The errors are all contained within the "Supported Memory Configurations" table, and specifically within the "SDRAM Organization" column.
Affected Technical Production Specifications:
NUC8i3BE/NUC8i5BE/NUC8i7BE - Table 4
NUC7CJY/NUC7PJY - Table 4
NUC7i7DN - Table 3
NUC7i5DN - Table 3
NUC7i3DN - Table 3
NUC7i5BNB/NUC7i7BNB - Table 4
NUC7i3BNB - Table 4
NUC6CAYB - Table 4
Following image illustrates the incorrect SDRAM configuration info (in red) in the table and the corresponding corrections (in purple).
The data in table in TPS are correct. Your interpretation is wrong. Only 4Gbit and 8Gbit SDRAM elements are supported. For example in first line in the table SODIM of 2GByte capacity. This SODIMM consist of 4 SDRAM elements, located on one side. Each SDRAM has capacity of 512MBytes = 512 x 8 = 4096 Mbit = 4Gbit.
I disagree that my interpretation is wrong.
SDRAM density (e.g. 4 Gbit or 8 Gbit) is clearly correctly covered in the "SDRAM Density" column of the table.
SDRAM chip count is correctly covered in the "Number of SDRAM Devices" column at far right.
Since DDR4 SODIMMs all have 64-bits of data (excluding ECC SODIMMs which have x72), a 2GB module using only 4 chips means that each chip must provide 16 bits of data.
Therefore, the SRAM Organization of "512M x4" which implies the chips have only 4 data bits each, totaling only 16 bits (4 x 4) of data is in error. Even if the SDRAM Organization is "512M x8", 4 of these will total only 32 bits of data which is still not enough to make a DDR4 SODIMM.
Also, a "512M x4" SDRAM as listed in the table is a 2Gbit device, not a 4Gbit device, so listing "512M x4" and 4Gbit SDRAM density in the same row is incorrect.
I personally use a number of Samsung M471A5244CB0-CRC DDR4 SODIMMs with my NUCs. These are 4GB, with just 4 chips on the top side. Each SDRAM chip is 512M x16 (8 Gbit) with 16 data bits each, totaling to 64 bits for the whole module, which is both single-sided and single-ranked. I confirmed this particular SDRAM chip as having 16 data bits using the datasheet from Samsung. This module is covered in the 3rd row of the table, and I provided the correction of the SDRAM organization to "512M x16".
I really believe the "x4" and "x8" listed in the "SDRAM Organization" column should not be interpreted as SDRAM chip count on each side of the module. These "x4" and "x8" refer to the data width of the SDRAM.