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哈囉大家好,我想問如何在Quartus II上產生傳播延遲,使用verilog #10寫法在編譯時會被忽略,請問有甚麼做法可以解決這個問題呢?

JSyu1
Beginner
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Abe
Valued Contributor II
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Propagation delays in Verilog like #10 are non-synthesizable and Quartus ignores delays coded in Verilog. If you really need to introduce a delay in a particular logic net, you will have to use buffers (ALTBUFF) components and specify the delay type. Another method of introducing delays could be via pipe-lining. Add a register in the circuit path and try getting the delay to the exact value needed.

JSyu1
Beginner
367 Views

我會嘗試用pipe-lining的方法,謝謝你的回答​

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