Link Copied
Propagation delays in Verilog like #10 are non-synthesizable and Quartus ignores delays coded in Verilog. If you really need to introduce a delay in a particular logic net, you will have to use buffers (ALTBUFF) components and specify the delay type. Another method of introducing delays could be via pipe-lining. Add a register in the circuit path and try getting the delay to the exact value needed.
我會嘗試用pipe-lining的方法,謝謝你的回答
For more complete information about compiler optimizations, see our Optimization Notice.