Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16347 Discussions

14566 The Fitter cannot place 5 periphery component(s) due to conflicts with existing constraints


In Platform Designer, for the Arria 10 Hard Processor System, in Tab "IP Selection", I have set GPIO = 5.

In Tab "Advanced Pin Placement", for HPS Shared I/Os, I have the following selections:

Q1_12: GPIO0:IO11

Q4_2:   GPIO1:IO13

Q4_5:   GPIO1:IO16

Q4_8:   GPIIO1:IO19

Q4_11: GPIO1:IO22 

In my ghrd file, in the top module, I have declared the signals:

inout wire bsm_led1,
inout wire bsm_led2,
inout wire bsm_led3,
inout wire bsm_led4,
inout wire gpio_tp,


I have instantiated the Platform Designer created file and I have connected the top level signals as follows:

.hps_io_hps_io_gpio_gpio1_io22 (bsm_led1),
.hps_io_hps_io_gpio_gpio1_io16 (bsm_led2),
.hps_io_hps_io_gpio_gpio1_io13 (bsm_led3),
.hps_io_hps_io_gpio_gpio1_io19 (bsm_led4),
.hps_io_hps_io_gpio_gpio0_io11 (gpio_tp),


In the .qsf files I have the following constraints:

set_location_assignment PIN_H17 -to bsm_led1
set_location_assignment PIN_F17 -to bsm_led2
set_location_assignment PIN_G19 -to bsm_led3
set_location_assignment PIN_K17 -to bsm_led4
set_location_assignment PIN_D18 -to gpio_tp


The fitter gives errors for all these signals. I am listing the errors for one of them:

Error (14566): The Fitter cannot place 5 periphery component(s) due to conflicts with existing constraints (5 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (84, 97) to (84, 98), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): bsm_led1
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info (175015): The I/O pad bsm_led1 is constrained to the location PIN_H17 due to: User Location Constraints (PIN_H17)
Info (14709): The constrained I/O pad is contained within this pin
Error (175005): Could not find a location with: IO_FUNCTION of HPS_IO (1 location affected)
Info (175029): H17

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2 Replies
Honored Contributor III

Since those are dedicated pins for the HPS that you specify in the HPS IP parameters, I'm not sure if you need the location assignments.  Did you try removing them?

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Hi Costas,

Based off the error messages the reason the pin placement fails is because the pin is already used by a different port. Can you try to remove the pin assignment perhaps let the Quartus auto assign the pin location?

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