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3-Wire SPI IP Component with Arria 10

Rleduc
New Contributor I
1,483 Views

Hello dear community,

 

I am using Quartus Prime Pro 22.4 / Arria 10 board, and I need to implement in my QSYS design a 3 wire SPI to communicate with external ADC (AD9250). I can only find the "SPI (4 Wire Serial) IP in the IP Catalog, and never 3 wire version. I saw the 3 wire option could exist from here: https://www.intel.com/content/www/us/en/docs/programmable/683113/21-3-19-2-0/spi-master.html , but I cannot find this 3 wire option anywhere now.

Can someone tell me where I can be provided a 3 wire serial SPI ?

 

Thanks,

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ShengN_Intel
Employee
1,445 Views

Hi,


Check this link https://www.intel.com/content/www/us/en/docs/programmable/683113/21-3-19-2-0/generating-the-design.html

At Example Design tab, Select Design and enable Generate 3-wire SPI module then Generate Example Design. You should see 3-wire SPI module spi_3wire.v being generated.


Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.


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3 Replies
ShengN_Intel
Employee
1,446 Views

Hi,


Check this link https://www.intel.com/content/www/us/en/docs/programmable/683113/21-3-19-2-0/generating-the-design.html

At Example Design tab, Select Design and enable Generate 3-wire SPI module then Generate Example Design. You should see 3-wire SPI module spi_3wire.v being generated.


Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.


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Rleduc
New Contributor I
1,432 Views

Hi,

 

Thank you very much for your insight. I could manage to generate the 3-wire SPI module. However I find myself stucked when compiling, after having added the 3-wire SPI either in my top.sv or directly in the qsys design. I included the necessary files in the project navigator, and I get the following error during Analysis & Synthesis stage :

Illegal connection found on I/O output buffer primitive u0|myspi_3wire_0|myspi_3wire_0|u_sdio|gpio_0|core|i_loop[0].altera_gpio_bit_i|output_buffer.obuf to u0|myspi_3wire_0|myspi_3wire_0|u_sdio|gpio_0|core|i_loop[0].altera_gpio_bit_i|input_buffer.ibuf. The IO output buffer should only drive out to a top-level pin.

 This comes from the "alteria_gpio.sv file. I believe this may just be because I added in a wrong way the 3-wire SPI IP generated from ed ?

 

Regards

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Rleduc
New Contributor I
1,430 Views

It's ok I found out that I need to directly connect SDIO or any bidirectionnal port to top level IO (FPGA pin) and not through wire !

 

I close this topic, thanks again

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