ALT_SLD_FAB Errors

[Altera_Forum]

Hello, 

 I have been using FPGAs and CPLDs up to some extent in industrial applications. Just out of curiosity, I have been trying to implement a NIOS II system following the exact same steps in the NIOS II Hardware Development Tutorial (tt_nios2_hardware_tutorial.pdf) available online. When I click on Start Analysis & Elaboration, I keep getting three errors related to ALT_SLD_FAB. The error messages are listed below:  Error (11176): Set_instance_parameter_value: There is no parameter named DESIGN_HASH on instance alt_sld_fab   Error (11176): Alt_sld_fab.: version not allowed for EModuleProperty, must be in {[DESCRIPTION, NAME, VERSION, MODULE_TCL_FILE, MODULE_DIRECTORY, INTERNAL, HIDE_FROM_SOPC, HIDE_FROM_QSYS, HIDE_FROM_QUARTUS, OPAQUE_ADDRESS_MAP, GROUP, AUTHOR, ICON_PATH, DISPLAY_NAME, DATASHEET_URL, TOP_LEVEL_HDL_FILE, TOP_LEVEL_HDL_MODULE, INSTANTIATE_IN_SYSTEM_MODULE, EDITABLE, VALIDATION_CALLBACK, EDITOR_CALLBACK, ELABORATION_CALLBACK, GENERATION_CALLBACK, COMPOSITION_CALLBACK, PARAMETER_UPGRADE_CALLBACK, OUTDATED_IP_FILE, ANALYZE_HDL, STATIC_TOP_LEVEL_MODULE_NAME, FIX_110_VIP_PATH, SUPPORTED_DEVICE_FAMILIES, REPORT_TO_TALKBACK, ALLOW_GREYBOX_GENERATION, SUPPRESS_WARNINGS, STRUCTURAL_COMPOSITION_CALLBACK, NATIVE_INTERPRETER, PREFERRED_SIMULATION_LANGUAGE, REPORT_HIERARCHY, UPGRADEABLE_FROM]}  Error (12154): Can't elaborate inferred hierarchy "sld_hub:auto_hub"  This is the first time I encountered such errors. I did some internet reserch, however, was not able to find any solution to this problem. If anyone who has encountered this and was able to solve the problem successfully could guide me through this problem, I would greatly appreciate it.

[Altera_Forum]

This sounds like it's related to SignalTap. If the design is instrumented with SignalTap you might try removing it and see if the error goes away. That would at least help isolate the problem for you.

[Altera_Forum]

Thank you for the quick reply. In the design, SignalTap is turned off. 

 Just to see how it goes, I tried to generate a few different designs with Qsys. Other than NIOS II, I tried generating a Quad SPI controller, a Triple-Speed Ethernet, an SPI unit and an on-chip RAM block, just to see if Quartus will compile. Qsys successfully generated all the components and I added them to the top level .bdf file one at a time and run Analysis & Synthesis. Except for the SPI and RAM implementation, all the other attempts gave the same three error messages. SPI and RAM, on the other hand, were successfully synthesized. Apparently, it is not directly related to Qsys either.  I am using Quartus 15.0 Web Edition. Could this be a licencing issue?