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Hi,
According to the spec, the maximum frequency of 133MHz is allowed. You will probably see a timing violation if you compile with frequency higher than the maximum allowable frequency.
Thanks.
Best regards,
KhaiY
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Hi,
May I know if you have any updates?
Thanks.
Best regards,
KhaiY
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We wrote verilog Code to replace the "DDIO_IN" IP. We've got it. Thank you!
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