ALTPLL error

[Altera_Forum]

Hello, 

  I have a problem when I try to simulate the PLL generated by the Megawizard tool of Quartus II. I used the ALTPLL megafunction with a simple clock input at 100MHz and an output at 200MHz (tried other frequency too) and I tried to simulate the output VHDL file.  To do so, I am using Modelsim (provided by altera). I set the input clock to 100MHz and when I run the simulation, all the output are 'undefined'. When I try to use the 'areset' signal, it generates a fatal error and stop the simulation as soon as 'areset' goes from 1 to 0.  I also tried to simulate it on Quartus but outputs are also undefined.  Can someone explain me how to make the PLL work?  Many thanks,  Nicolas

[Altera_Forum]

Maybe the outputs are undefined because you haven't run the simulation long enough for the PLL simulation model to simulate the PLL locking. It won't necessarily take as long as it takes the real hardware to lock, but as I recall it can take multiple clock cycles. 

 If the "fatal error" was an internal error, you should file a service request. If it was a regular error message in the Quartus GUI, try right clicking the message and selecting Help. Sometimes the help pages for messages give you the clue you need to figure out the cause.

[Altera_Forum]

I think that you need to change the time from nS to pS.

[Altera_Forum]

@Brad : I did run the simulation for quite a lot of time but no change. Actually I'm simulating on Modelsim and here is the result I get : 

 http://img179.imageshack.us/img179/4843/pllaj9.jpg   I do not assert areset because it makes error and it should not be a problem to lock the PLL. The code is attached and is a simple PLL generated by Quartus II megafunction. The PLL is just supposed to output the same clock frequency as the input one.  As you can see, subwire1 and subwire0(0) has X values and I dont know why.   LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY pll IS PORT ( areset : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END pll; ARCHITECTURE SYN OF pll IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT altpll GENERIC ( clk0_divide_by : NATURAL; clk0_duty_cycle : NATURAL; clk0_multiply_by : NATURAL; clk0_phase_shift : STRING; compensate_clock : STRING; gate_lock_signal : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; invalid_lock_multiplier : NATURAL; lpm_type : STRING; operation_mode : STRING; port_activeclock : STRING; port_areset : STRING; port_clkbad0 : STRING; port_clkbad1 : STRING; port_clkloss : STRING; port_clkswitch : STRING; port_configupdate : STRING; port_fbin : STRING; port_inclk0 : STRING; port_inclk1 : STRING; port_locked : STRING; port_pfdena : STRING; port_phasecounterselect : STRING; port_phasedone : STRING; port_phasestep : STRING; port_phaseupdown : STRING; port_pllena : STRING; port_scanaclr : STRING; port_scanclk : STRING; port_scanclkena : STRING; port_scandata : STRING; port_scandataout : STRING; port_scandone : STRING; port_scanread : STRING; port_scanwrite : STRING; port_clk0 : STRING; port_clk1 : STRING; port_clk2 : STRING; port_clk3 : STRING; port_clk4 : STRING; port_clk5 : STRING; port_clkena0 : STRING; port_clkena1 : STRING; port_clkena2 : STRING; port_clkena3 : STRING; port_clkena4 : STRING; port_clkena5 : STRING; port_extclk0 : STRING; port_extclk1 : STRING; port_extclk2 : STRING; port_extclk3 : STRING; valid_lock_multiplier : NATURAL ); PORT ( inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); locked : OUT STD_LOGIC ; areset : IN STD_LOGIC ; clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire5_bv(0 DOWNTO 0) <= "0"; sub_wire5 <= To_stdlogicvector(sub_wire5_bv); sub_wire1 <= sub_wire0(0); c0 <= sub_wire1; locked <= sub_wire2; sub_wire3 <= inclk0; sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; altpll_component : altpll GENERIC MAP ( clk0_divide_by => 1, clk0_duty_cycle => 50, clk0_multiply_by => 1, clk0_phase_shift => "0", compensate_clock => "CLK0", gate_lock_signal => "NO", inclk0_input_frequency => 10000, intended_device_family => "Cyclone II", invalid_lock_multiplier => 5, lpm_type => "altpll", operation_mode => "NORMAL", port_activeclock => "PORT_UNUSED", port_areset => "PORT_USED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_configupdate => "PORT_UNUSED", port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_USED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", port_phasestep => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED", port_pllena => "PORT_UNUSED", port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED", port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_UNUSED", port_clk2 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", port_extclk0 => "PORT_UNUSED", port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED", valid_lock_multiplier => 1 ) PORT MAP ( inclk => sub_wire4, areset => areset, clk => sub_wire0, locked => sub_wire2 ); END SYN;   @Avatar : I dont get what you mean but I tried and nothing changes.

[Altera_Forum]

I have manage to simulate the PLL on quartus II. 

The functional simulation is working ie the output clocks are correct. The timing simulation is wrong : the output clocks have 'X' values.  Can someone explain me this ?  Many thanks

[Altera_Forum]

From the waveforms, it seems like the PLL is not getting locked somehow. Try extending the simulation time to see if it gets locked. You could regenerate the PLL using megawizard and start from the scratch to see if it works. Try with some other input/output frequencies to get the PLLs working and then go for your desired frequencies.

[Altera_Forum]

I managed to make it works on QuartusII. However, my whole design is being tested on Modelsim and its still not working. I'm using the same test vectors and it never locks.

[Altera_Forum]

I am not sure of my suggestion but you could give it a try. Start with areset "high" and then make it "low" after 1 or 2 clocks and i guess it should work. My guess is regarding initialisation of the clock and so on... in modelsim. Give a try and let me know, what happens. 

 Regards, Anil

[Altera_Forum]

The problem is that when I try to reset the PLL, I'm getting an error from Modelsim and simulation stops. I think this is happening when the PLL is designed for Cyclone II because I tried to use Stratix and the reset thing is ok. However, the PLL doesnt work for any of these. 

 I'm starting to think that my Modelsim has problem since the support told me it is ok for them. However I tried to re-install the stuff and nothing changed.

[Altera_Forum]

Have you tried the suggestion that Avatar recommended above? I had this same problem and this turned out to be the fix. The Altera models require you use the picosecond timescale for simulations.

[Altera_Forum]

Thank you very much! 

 It is finally working. It is indeed the timescale that was the problem. I did not understand what Avatar told me.  Many thanks Nicolas