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When I attempt to create a set of files for an ALTPLLin Quartus 23.1, the IP wizard leaves the "Next"-driven steps just before permitting configuration of an output, then writes an empty .qip file. What is the problem? Does someone have an example of an instantiation and entity/component of the ALTPLL in VHDL? Thanks!
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A known bug reported in several posts. Intel released a patch for 23.1 std but not yet for 23.1 lite. Present solution is to use PLL generation of previous version.
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey

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