Hi All,I am tying to create an ARRAY dynamic size with range of 1-64 (XXX). (I will use it for creating a dynamic data delay that can be configured) Modelsim compile it with no errors , but i don't see a change in the array size in the wave window. Can you help? ENTITY a2d IS PORT ( reset_n :in std_logic; clk :in std_logic; REG_CAN_DATA_A_DLY :in std_logic_vector (7 downto 0) --:="0000000000000001"; --:integer := 50; ); END; signal XXX :integer range 1 to 64; type delay_array is array(1 to XXX) of std_logic_vector(15 downto 0); signal data_delay_array : delay_array; begin XXX <= to_integer(unsigned(REG_CAN_DATA_A_DLY)); process ( reset_n,clk) begin if ( reset_n = '0') then elsif (clk'event and clk = '1') then data_delay_array <= data_in & data_delay_array( 1 to delay_array'high-1) ; data_in_delay <= data_delay_array(data_delay_array'high); end if; end process; END a2d;
You cannot resize an array inside FPGA logic - it makes no sense - you cannot add or remove resources while a design is running.If this is for testbenching ONLY, you can create dynamic arrays using access types - but from your design example, you seem to want an implementable design. Your array needs to be sized for the worst case possible, and then assign the parts of the array you need at any given time.
hi,Array size can be changed through generics to make your design scalable. But you can not create dynamic array which size depends on signal or port value. Here is my suggestion: Create array of length equal to your maximum wanted delay. Generate in series connected registers (input of first register is your wanted to delay signal, input of next register is connected to previous register output and so on). Then use mux to select one of the register outputs. But take in mind that if you are planing to use large array this will require large mux which will give delays trough comb elements in real hardware.