AVSPI Core Attributes Failure

[ESkul1]

In one of the AVSPI core files, spiphyslave.v, are several set_false_path attributes that are causing several warnings such as the following, during Compile:

/*local reg for shift register*/ 

(* altera_attribute = {"-name SDC_STATEMENT \"set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*]\" "} *) reg [7:0] rdshiftreg;   

Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <from> is an empty collection

Info (332050): run_legacy_fitter_flow

Since this is down inside a Quartus IP, is there a recommended way to handle this?

For example, should the core file(s) be modified by commenting out the failing set_false_path constraints and replace with corresponding SDC file constraints? This seems like a stretch, modifying a tool-generated core. Is there a more suitable solution?

Thank you.

[KhaiChein_Y_Intel]

Hi,

Can you provide the design for investigation? May I know which version of the software you are using?

Thanks.

[ESkul1]

HI, SW version is Quartus Prime, 16.1.2, Build 203 01/2017 SJ Lite Ed.

Part family is Max10.

I'm putting together a test case to upload right now; will post as soon as ready.

Thank you for the quick reply.

[ESkul1]

Archived project, Test_FalsePath attached.

Thank you.

[KhaiChein_Y_Intel]

Hi,

I have file a case to engineering. Thanks for reporting this to us.

Thanks.

[ESkul1]

Hello YY, can you provide any update info on this core constraint failure? My design can't be finalized until this core constraint issue is resolved. Thank you for your time and attention.

[KhaiChein_Y_Intel]

Hi,

I have yet to receive the reply from engineering. I have sent a follow-up note to the team and I will keep you posted. Thanks for your understanding.

Thanks.

[ESkul1]

OK, appreciate the update.

[ESkul1]

Hello YY, can you please provide a recommended work-around to resolve the constraint failures reported during Compile, inside the AVSPI core file, spiphyslave.v ?

I need to submit the design to production team as we are moving into production with this FPGA. I do not want to deliver product with possible timing defect.

Please try to understand I have a real deadline and need guidance on how to resolve this issue.

Thank you again for your time and help.

[KhaiChein_Y_Intel]

Hi,

I tried to follow-up with engineering but I have yet to receive the reply from the team. I will send a note to the team again to raise the urgency.

Thanks.

[KhaiChein_Y_Intel]

Hi,

1) This set_false_path -> set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*]  in MISO block is wrong.

This is fixed in 19.1std b659 onwards to -> set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*]

   Can you please either regenerate the RTL or replace the SDC content?

2) This set false path -> set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] is in MOSI block. 

   I noticed from the Technology map viewer that MOSI block doesn't exist (synthesize away). Did you not connect up mosi interface? If this is expected than this set_false_path can be ignored.  

Thanks.

[ESkul1]

HI KhaiY,

I tried the constraint you proivded, replaceing the original in the hdl file with the one you sent, as follows:

/*(* altera_attribute = {"-name SDC_STATEMENT \"set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*]\" "} *) reg [7:0] rdshiftreg;  */

(* altera_attribute = {"-name SDC_STATEMENT \"set_false_path -from [get_pins *] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*];

That produced a syntax error so I guess there is some syntax differences between the original and the new one that I have not done correctly?

Thank you again for your time and help.

[KhaiChein_Y_Intel]

Hi,

Did you upgrade the IP? It is regenerated automatically without the RTL modification.

Thanks.

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks