Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

About SignalTap

Yamada1
Beginner
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I'm trying to debug with signal tap, but I can't see the signal as I expected.

It would be helpful if you could give me advice on how to use the signal tap.

I am using Quartus Prime Standard Edition 18.1.1.

The stp file is created by the following procedure.

1) Launch Signal Tap Logic Analyzer with a design that has completed fitting

2) Saving the stp1.stp file and registering it in the design

3) Clock specification

  Since incremental compilation is not performed, search with Signal Tap: pre-synthesis and specify the PLL output (outclk_0) in the design. (Unassigned is displayed in the Assignments column)

4) Specify data

  Search and specify with Signal Tap: pre-synthesis in the same way as the clock

5) Save the stp1.stp file and compile the design

 

Are there any deficiencies in the steps up to this point?

 

I'm sorry to trouble you, but it would be helpful if you could teach me.

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RichardTanSY_Intel
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In most cases, you choose a clock that is in the same clock domain with the signal that you are looking at. But there is no requirement for that. Sometimes you might use a faster clock domain for a slower signal, to get a higher sampling rate.

You can use the fastest clock available to get the best results.

Refer to the Timing Analysis section of the Compilation Report for the maximum frequency of the logic analyzer clock.


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RichardTanSY_Intel
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I assume Step 4 Specify the data - mean to set the trigger condition and the signal configuration. If so, I think so far so good.

Btw, we have a tutorials on "SignalTap with Verilog Designs"

Find "Signal Tap Logic Analyzer " @ https://fpgacademy.org/tutorials.html > Click Verilog or VHDL to download the file.


You can go through the tutorial to get familiar with it.


There also instructor-led class on Signal Tap, next week. (although the time may not be friendly but it is highly recommended)

https://learning.intel.com/Developer/learn/course/internal/view/classroom/1066/signal-tap


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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Yamada1
Beginner
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Thank you for answering.

Step 4 is to specify the signal configuration and trigger to be monitored.

This means that there is no problem with the method of creating the stp1.stp file itself.

 

The current problem here is the following.

 1) When I check the signal output to the IO pin as a monitor with an oscilloscope, it works properly, but when I look at it with Signal Tap, it doesn't show the same waveform as the oscilloscope. (Signal Tap does not look directly at the output pin, but looks at the signal connected to it.)

 2) The system clock is 20MHz (generated by the PLL) and what you want to check is its synchronization circuit. The internal operation runs at 1MHz, but the timing generation etc. are performed with a pulse of 50ns width. If you try to trigger with this 50ns pulse, the trigger will not work. It is the same as 1) that it works normally when output to the IO pin as a monitor.

 

It is recommended that the Signal Tap clock be at least twice the signal, but in the above case, does the Signal Tap clock need to be at least 40MHz?

I will check the presented materials from now on, but if you have any suggestions, it would be helpful if you could let me know.

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RichardTanSY_Intel
602 Views

In most cases, you choose a clock that is in the same clock domain with the signal that you are looking at. But there is no requirement for that. Sometimes you might use a faster clock domain for a slower signal, to get a higher sampling rate.

You can use the fastest clock available to get the best results.

Refer to the Timing Analysis section of the Compilation Report for the maximum frequency of the logic analyzer clock.


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Yamada1
Beginner
591 Views

Thank you for answering.

I didn't realize about the maximum frequency of the logic analyzer clock. Thank you for your advice.

I understand that depending on the design of the signal tap, the clock to be used may interrupt the maximum frequency.

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RichardTanSY_Intel
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Thank you for acknowledge the solution provided. 

 I’m glad that your question has been addressed, I now transition this thread to community support. 

Thank you.


Best Regards,

Richard Tan


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