About signal and variable

[Altera_Forum]

I just start using VHDL for one month, I am a little confused by signal and variable. 

 I read the textbook, I know the difference between them like:  Variable is a local one can be used inside process where it is declaration.  Variable can be assigned an initial value while signal can but only in simulation. Both of them can be synthesised.  But I am not clear is when I should use signal, and when I should use variable. Is there any rules I should follow? If someone can take some simple examples, that will be very helpful for me to understand.  Thanks in advance.

[Altera_Forum]

Yes, as a beginner, only use signals. variables will confuse you. 

 The actual difference is that signals are only scheduled to be updated when a process suspends and takes the last value assigned to it, but a variable is updated immediatly. These differences in behavior can lead to things that look odd to people that dont understand.   signal a : integer := 0; --there is nothing wrong with giving an initial value to a signal. It should synthesise fine as the power up value process(clk) variable b : integer := 0; begin if rising_edge(clk) then a <= 10; a <= a + 90; a <= a + 1; b := 10; b := b + 90; b := b + 1; end if; end process;   In this code, if you simulated it, you would see a start at 0 and increment by 1 on every clock cycle because the assignmnet of 10 and +90 are overriden by the a+1 assignment. b would just be constant at 101 forever. Variables can be used to synthesise the same hardware as signals (mostly) but then your code ordering has much more of an effect.  So - general rule - dont use variables until you know more about VHDL. Stick with signals for now.

[Altera_Forum]

--- Quote Start ---  I just start using VHDL for one month, I am a little confused by signal and variable.  I read the textbook, I know the difference between them like:  Variable is a local one can be used inside process where it is declaration.  Variable can be assigned an initial value while signal can but only in simulation. Both of them can be synthesised.  But I am not clear is when I should use signal, and when I should use variable. Is there any rules I should follow? If someone can take some simple examples, that will be very helpful for me to understand.  Thanks in advance.  --- Quote End ---    The way I think of a variable (inside a vhdl process at least) is that it allows combinatorial parts(and hence quick decision). Remember every signal assignment inside a clocked process infers logic of your assignment right hand followed by a register. for example: value1 <= temp + 1; means an adder followed by the register value1.  But at times you might need value1 to get the temp + 1 before going through a register delay. In this case you declare as variable then: value1 := temp + 1; gets adder result for target without delay.

[Altera_Forum]

Thanks very much, both of you. 

 I can try to avoid using variables, but this may not help in long term since if I keep avoid it, how can I know how to use it?   kaz, your conclusion is very interesting. Since variable can be only used in a process (where it is declared). If this process is a sequential logic (sensitivity list is a clock and trigger by edge) , then signal is used for registers while variables is used for combinatorial logic. But if this is already a combinatorial logic process, then signal and variable will be same. Is that my understanding basically right?  Thanks very much.

[Altera_Forum]

--- Quote Start ---  Thanks very much, both of you.  I can try to avoid using variables, but this may not help in long term since if I keep avoid it, how can I know how to use it?   kaz, your conclusion is very interesting. Since variable can be only used in a process (where it is declared). If this process is a sequential logic (sensitivity list is a clock and trigger by edge) , then signal is used for registers while variables is used for combinatorial logic. But if this is already a combinatorial logic process, then signal and variable will be same. Is that my understanding basically right?  Thanks very much.  --- Quote End ---    Basically I think so.   Let me reword my view of variable Versus signal within a clocked process.  When node A is signal then A <= B and C; infers a circuit of B and C followed by register A (comb. then register). when node A is variable then A:= B and C; infers a circuit of B and C => A (comb. only)  Whether then you get a register at final compilation depends.   If value of A variable is used later in another statement within process e.g. A := B and C; D <= A;  then no register is inferred to save A. comb. of B and C => A is inferred followed by D register.  If value of (A) is used before its assignment e.g. D <= A; A := B and C;   then it implies registering node A to start of process then applying it to D. Thus I assume you may get two registers now D and that outputting A.  In non clocked process(comb) I don't expect much difference between using signal or variable but behaviorally it remains that the variable is meant to acquire its value without update at end of process.  All above is my personal view and may be verified by simple experiments(that I haven't done)

[Altera_Forum]

That is correct Kaz, and hence why I suggest sticking with signals until you're confident with VHDL. Variable placement makes all the difference when it comes to infering logic, getting code in the wrong order can cause you problems or infered latches, or just no logic at all. 

 IIRC, this code could be the cause for some problems as the synthesisor is likely to infer a constant, whereas the simulation would show a counter.   process(clk) variable : a := integer 0; begin if rising_edge(clk) then a := a + 1; op <= a; end if; end process;   Because the register element lives with the op signal, not with a, and as a is initialised to 0, there is no storage associated with a and hence drives a constant 1.  but if you changed it to a := op + 1;  it would work fine, as a is the sum of the register and 1.

[Altera_Forum]

--- Quote Start ---  In non clocked process(comb) I don't expect much difference between using signal or variable but behaviorally it remains that the variable is meant to acquire its value without update at end of process.  --- Quote End ---   The different behaviour of variables and signals also matters in a pure combinatorial process if you have multiple assignments to the variable respectively signal.

[Altera_Forum]

--- Quote Start ---  That is correct Kaz, and hence why I suggest sticking with signals until you're confident with VHDL. Variable placement makes all the difference when it comes to infering logic, getting code in the wrong order can cause you problems or infered latches, or just no logic at all.   --- Quote End ---    Indeed. In all the so many years of work I have never needed to use variable except once. Here its is:   -- basically a clocked process variable counter : unsigned(12 downto 0) := (others => '0'); ... counter := counter + unsigned(increment); if counter > 3071 then -- wrap up at overflow counter := counter - to_unsigned(3072,12); end if; addr <= std_logic_vector(counter); ...   It is an accumulator that adds increment value modulo 3072(for NCO etc). The counter must be checked for overflow but should not overflow! instead it should wrap up. So it needs to be prejudged. Though one can use a second counter(that looks ahead) but a variable is useful here. if you use signal it will overflow first then wrap up which is not right in this case.

[Altera_Forum]

--- Quote Start ---  The different behaviour of variables and signals also matters in a pure combinatorial process if you have multiple assignments to the variable respectively signal.  --- Quote End ---    I do expect some differences but I am not sure if it has any practical benefit in order to use variable in a comb. process.

[Altera_Forum]

--- Quote Start ---  I do expect some differences but I am not sure if it has any practical benefit in order to use variable in a comb. process.  --- Quote End ---    It can affect the ordering of any logic, and if variables are placed after a signal assignment (that then affect the signal) latches may be produced.

[Altera_Forum]

Thanks so much, all of you. 

 So generally speaking, it looks like variable is unecessary in most cases, right?  In sequential process, I can use signals to make the pipeline. I don't have to put variable between them like:   A := B and C; D <= A;  can be:  D<= B and C;  For pure combinatorial logic, I even don't use process. I will use direct assignment out of process like:  A<= B and C;  This is similar as I wrote Verilog, I never use "always" to write combinatorial logic, I use "assign" like "assign A<= B & C".

[Altera_Forum]

Thats correct. you dont need variables in most cases. The only time you may want to use them is to break down complicated assigments to make the more readible, or you will have to use them in functions and procedures (again, mainly used for readability). 

 But when it comes to testbenches - go wild. (ie. variables become very useful).

[Altera_Forum]

Thanks very much, Tricky.