About timing constraints of ‘in2out’ timing path

[Altera_Forum]

Q: About timing constraints of‘in2out’ timing path 

 My design is as follows: file:///C:/Users/dell/AppData/Local/Temp/msohtml1/01/clip_image002.gif  In my design, there are three ports: clk(system clock), ina(input port), outb(output port). My constraints are as follows:  create_clock -period 10 -name my_clk [get_ports clk]  set_input_delay -max 3 -clock my_clk [get_ports ina]  set_ouput_delay -max 3 -clock my_clk [get_ports outa]  set_max_delay 2 -from ina -to outb When Quartus tools analysis the 3rd timing path, the required time calculated as follows: 3(input_delay) + 3(output_delay) + 2(max_delay) + tdelay(com logic delay) <10(clock cycle) But I want to constraint the delay less than 2ns from ‘ina’ to ‘outb’, I don’t know how to constraint the timing path, could you please give me some advise for this case?   Thanks   wuyu

[Altera_Forum]

--- Quote Start ---  Q: About timing constraints of‘in2out’ timing path   My design is as follows: file:///C:/Users/dell/AppData/Local/Temp/msohtml1/01/clip_image002.gif  In my design, there are three ports: clk(system clock), ina(input port), outb(output port). My constraints are as follows:  create_clock -period 10 -name my_clk [get_ports clk]  set_input_delay -max 3 -clock my_clk [get_ports ina]  set_ouput_delay -max 3 -clock my_clk [get_ports outa]  set_max_delay 2 -from ina -to outb When Quartus tools analysis the 3rd timing path, the required time calculated as follows: 3(input_delay) + 3(output_delay) + 2(max_delay) + tdelay(com logic delay) <10(clock cycle) But I want to constraint the delay less than 2ns from ‘ina’ to ‘outb’, I don’t know how to constraint the timing path, could you please give me some advise for this case?   Thanks   wuyu  --- Quote End ---    May I ask what is the thinking here? you have an input (ina) going direct to output (outb) through some comb. logic that receives a registered version of ina(call it ina_r).  So ina_r will get sampled at clock edge running every 10 ns yet you want ina to outb < 2ns???

[Altera_Forum]

--- Quote Start ---    create_clock -period 10 -name my_clk [get_ports clk]  set_input_delay -max 3 -clock my_clk [get_ports ina]  set_ouput_delay -max 3 -clock my_clk [get_ports outa]  set_max_delay 2 -from ina -to outb When Quartus tools analysis the 3rd timing path, the required time calculated as follows: 3(input_delay) + 3(output_delay) + 2(max_delay) + tdelay(com logic delay) <10(clock cycle) But I want to constraint the delay less than 2ns from ‘ina’ to ‘outb’,  --- Quote End ---    You're already constraining that. You're giving TimeQuest two sets of constraints - tdelay < 2.0 from the set_max_delay constraint. - 3 + tdelay + 3 < 10, from the set_input_delay and set_output_delay constraints.  That said, achieving a 2.0 ns delay is going to be hard, if not impossible.

[Altera_Forum]

I'm sorry for the description fault, the tool calculate the required time is as follows: 

2ns(max_delay) - 3ns(output_delay) = -1ns;  And the arrived time is as follows:  3ns(input_delay) + tDELAY;  So tools think the constraints should be:  3ns(input_delay) + tDELAY < -1ns => tDELAY <-4ns;  But my thinking is that I want to constraint the max delay time is 2ns from ina to oub (tDELAY < 2ns), so, for that, I need to constraint the max_delay is 8ns;  It is right?   --- Quote Start ---  May I ask what is the thinking here? you have an input (ina) going direct to output (outb) through some comb. logic that receives a registered version of ina(call it ina_r).  So ina_r will get sampled at clock edge running every 10 ns yet you want ina to outb < 2ns???  --- Quote End ---  

[Altera_Forum]

I'm sorry for the description fault, the tool calculate the required time is as follows: 

2ns(max_delay) - 3ns(output_delay) = -1ns;  And the arrived time is as follows:  3ns(input_delay) + tDELAY;  So tools think the constraints should be:  3ns(input_delay) + tDELAY < -1ns => tDELAY <-4ns;  But my thinking is that I want to constraint the max delay time is 2ns from ina to oub (tDELAY < 2ns), so, for that, I need to constraint the max_delay is 8ns;  It is right?   --- Quote Start ---  I'm sorry for the description fault, the tool calculate the required time is as follows:  2ns(max_delay) - 3ns(output_delay) = -1ns;  And the arrived time is as follows:  3ns(input_delay) + tDELAY;  So tools think the constraints should be:  3ns(input_delay) + tDELAY < -1ns => tDELAY <-4ns;  But my thinking is that I want to constraint the max delay time is 2ns from ina to oub (tDELAY < 2ns), so, for that, I need to constraint the max_delay is 8ns;  It is right?  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  I'm sorry for the description fault, the tool calculate the required time is as follows:  2ns(max_delay) - 3ns(output_delay) = -1ns;  And the arrived time is as follows:  3ns(input_delay) + tDELAY;  So tools think the constraints should be:  3ns(input_delay) + tDELAY < -1ns => tDELAY <-4ns;  But my thinking is that I want to constraint the max delay time is 2ns from ina to oub (tDELAY < 2ns), so, for that, I need to constraint the max_delay is 8ns;  It is right?  --- Quote End ---    I don't see how you found out what the tool is thinking. set_input_delay has nothing to do with tdelay path. It is meant for register path only, so is set_output_delay. And in both cases it has nothing to do with concept of pure delay. set_input_delay is information to the tool about data/clock offset arriving at pins. set_output_delay is information to the tool about allowed range of data/clock offset ejected at output pin. The path of tdelay is comb. from pin to pin and I suppose it will be dealt with independant of register path. Whether you get it or not is up to your luck but still I don't understand the merits of your approach from basic design perspective. May be you tell us what is the purpose of your constraints...

[Altera_Forum]

Thanks for your help. And this case is only my little example from my all design.  

I try to clear this question through Design Compiler in Synopsys, and I have found  the way to solve my constraints question. The setup calculate is as follows:  Required time: Value(max_delay) - Value(output_delay=3ns);  Arrived time: Value(input_delay=3ns) + tdelay;  Setup ensure: Arrived time <= Required time  So, if I want to constraint the tdelay max 2ns, the result is that we should constraint the max_delay 8ns.  set_max_delay 8 -from ina -to outb  No matter at all, thanks. Hope we could commucation more latter.    --- Quote Start ---  I don't see how you found out what the tool is thinking. set_input_delay has nothing to do with tdelay path. It is meant for register path only, so is set_output_delay. And in both cases it has nothing to do with concept of pure delay. set_input_delay is information to the tool about data/clock offset arriving at pins. set_output_delay is information to the tool about allowed range of data/clock offset ejected at output pin. The path of tdelay is comb. from pin to pin and I suppose it will be dealt with independant of register path. Whether you get it or not is up to your luck but still I don't understand the merits of your approach from basic design perspective. May be you tell us what is the purpose of your constraints...  --- Quote End ---