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MZann1
Beginner
147 Views

Adding a new signal in chip planner

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Hello,

I have inherited an old design on cyclone 2 FPGA and would like to add a new signal without affecting the place and route of the old design.

The signal I want to add is simply connecting two pins in different entities.

Is there any way to do this change in chip planner for example? or using logiclock is the only option here?

Any suggestion is appreciated. 

Regards,

Mahmoud

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sstrell
Honored Contributor II
129 Views

In theory, you could make an ECO change in the Chip Planner to do this so it would be present in a new programming file you generate, but this can be tricky to do (finding the resources, manually enabling the routing resources needed to make the connection, etc.) especially if you're not familiar with Chip Planner and the Resource Property Editor.  It is possible, though.  Logic Lock has nothing to do with it.

#iwork4intel

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4 Replies
sstrell
Honored Contributor II
130 Views

In theory, you could make an ECO change in the Chip Planner to do this so it would be present in a new programming file you generate, but this can be tricky to do (finding the resources, manually enabling the routing resources needed to make the connection, etc.) especially if you're not familiar with Chip Planner and the Resource Property Editor.  It is possible, though.  Logic Lock has nothing to do with it.

#iwork4intel

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MZann1
Beginner
123 Views

Thanks sstrell,

 

I have seen many video/tutorials on chip planner but non of them shows how to make new connections in the design, is there any video/tutorial you can suggest?

 

I though with logiclock I can lock the old design and add my new signal afterwards, in this case the old design should be left untouched?

 

Regards,

Mahmoud

sstrell
Honored Contributor II
114 Views

No, I've never made that type of change as an ECO and it's not really recommended.  Your best bet would be to look through documentation and help for the Resource Property Editor to see if it's possible.

As for Logic Lock, that's not what it's used for.  Logic Lock is used to force the Fitter to place selected entities in a design in a physical location on the chip, usually to help with timing closure or for more advanced design flows (like partial reconfiguration).  You may be thinking of incremental compilation, which can lock down the post-fit netlist, but it would still require you to go back to the design, create design partitions, add the new connection in a new partition and recompile the design, which defeats the purpose of what you want to do.

#iwork4intel

MZann1
Beginner
105 Views

The design I inherited does not meet the timing constraints, but has been working for years

I am not keen to modify it in anyway.

The signal is already there in the design it is just need to be connected to one pin of a nios processor.

ECO seems the only way to do it.

 

Thanks,

Mahmoud