Agile X Transciever Design (JESD204C + F-tile) HSSI_PLD_ADAPT_RX_CLUSTER error

[mschiller-nrao]

How do I correct this error?  I do not believe I'm constraining this device as it's in the Auto Tiles.

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_PLDADAPT_RX_CLUSTER(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic HSSI_PLDADAPT_RX_CLUSTER in region (11, 229) to (11, 252), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The HSSI_PLDADAPT_RX_CLUSTER name(s): ghrd_agib027r31b1e1vaa_auto_tiles|z1577b_x5_y166_n0|hdpldadapt_rx_chnl_21~HSSI_PLDADAPT_RX_CLUSTER1
Error(16234): No legal location could be found out of 8 considered location(s). Reasons why each location could not be used are summarized below:
Info(175013): The HSSI_PLDADAPT_RX_CLUSTER is constrained to the region (11, 229) to (11, 252) due to related logic
Info(175015): The HSSI_Z1577B ghrd_agib027r31b1e1vaa_auto_tiles|z1577b_x5_y166_n0|z1577b is constrained to the region (5, 166) to (5, 166) due to: User Location Constraints (Z1577B_X5_Y166_N0)
Info(14709): The constrained HSSI_Z1577B drives this HSSI_PLDADAPT_RX_CLUSTER
Error(175006): There is no routing connectivity between the HSSI_PLDADAPT_RX_CLUSTER and destination HSSI_Z1577B
Info(175027): Destination: HSSI_Z1577B ghrd_agib027r31b1e1vaa_auto_tiles|z1577b_x5_y166_n0|z1577b
Info(175015): The HSSI_Z1577B ghrd_agib027r31b1e1vaa_auto_tiles|z1577b_x5_y166_n0|z1577b is constrained to the region (5, 166) to (5, 166) due to: User Location Constraints (Z1577B_X5_Y166_N0)
Error(175022): The HSSI_PLDADAPT_RX_CLUSTER could not be placed in any location to satisfy its connectivity requirements
Info(175021): The destination HSSI_Z1577B was placed in location HSSIZ1577B_X5_Y166_N0
Info(175029): 6 locations affected
Info(175029): HSSI_PLDADAPT_RX_CLUSTER containing HSSIAIBNDRX_1M4
Info(175029): HSSI_PLDADAPT_RX_CLUSTER containing HSSIAIBNDRX_1M5
Info(175029): HSSI_PLDADAPT_RX_CLUSTER containing HSSIAIBNDRX_1N0
Info(175029): HSSI_PLDADAPT_RX_CLUSTER containing HSSIAIBNDRX_1N1
Info(175029): HSSI_PLDADAPT_RX_CLUSTER containing HSSIAIBNDRX_1N2
Info(175029): HSSI_PLDADAPT_RX_CLUSTER containing HSSIAIBNDRX_1N4
Error(175006): There is no routing connectivity between the HSSI_PLDADAPT_RX_CLUSTER and destination HSSI_PLDADAPT_RX
Info(175027): Destination: HSSI_PLDADAPT_RX ghrd_agib027r31b1e1vaa_auto_tiles|z1577b_x5_y166_n0|hdpldadapt_rx_chnl_22
Info(175013): The HSSI_PLDADAPT_RX is constrained to the region (11, 232) to (11, 232) due to related logic
Info(175015): The HSSI_Z1577B ghrd_agib027r31b1e1vaa_auto_tiles|z1577b_x5_y166_n0|z1577b is constrained to the region (5, 166) to (5, 166) due to: User Location Constraints (Z1577B_X5_Y166_N0)
Info(14709): The constrained HSSI_Z1577B drives this HSSI_PLDADAPT_RX
Error(175022): The HSSI_PLDADAPT_RX_CLUSTER could not be placed in any location to satisfy its connectivity requirements
Error(175022): The destination HSSI_PLDADAPT_RX could not be placed in any location to satisfy its connectivity requirements
Info(175029): 1 location affected
Info(175029): HSSI_PLDADAPT_RX_CLUSTER containing HSSIAIBNDRX_1N5
Error(175006): There is no routing connectivity between the HSSI_PLDADAPT_RX_CLUSTER and destination core logic
Info(175027): Destination: core logic CORE_LOGIC_OF_ghrd_agib027r31b1e1vaa_auto_tiles|z1577b_x5_y166_n0|x0_x0_u23_2_hdpldadapt_pld_pma_internal_clk1_hioint
Error(175022): The HSSI_PLDADAPT_RX_CLUSTER could not be placed in any location to satisfy its connectivity requirements
Info(175021): The destination core logic was placed in location CORE_LOGIC
Info(175029): 1 location affected
Info(175029): HSSI_PLDADAPT_RX_CLUSTER containing HSSIAIBNDRX_1N3

[Harshx]

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate on this case and get back to you soon once I have any finding. Meanwhile can you please share the following info for my better understanding.

1. What's the version of Quartus you are using?
2. Can you share the related files so that I can compile and check for the same error?

Thanks for your patience.

Regards,

Harsh M

[mschiller-nrao]

This is in Quartus Prime Version 23.4.0 Build 79 dated 11/22/2023 SC pro Edition

(no patches installed)

The QAR file is attached

[Harshx]

Hi,

Your design is failing at Design analysis.

Error message:

VHDL error at memory_loader_pkg.vhd(124): file 'f_in' is not open

[mschiller-nrao]

My fault.  The QAR process didn't include the text file used to initialize a rom inside the design.

If you download the attached build_rom.txt and place it inside the DBE_proto folder (where the qpf/qsf are).  you should be able to build the design (at least to the original problem)...

[mschiller-nrao · Accepted solution]

So turns out if I use an external clock for my IOPLL the problem is resolved.

Dotted line is the configuration in the project above resulting in the error, solid line for userclk (reference to IOPLL) from another FPGA pin works fine: