Hi,I am using ALTCLKCTRL to mux two clock signals. One of the signal is a PLL output and the other one is an from the clock pin. I get an error from the fitter stating that it cannot place a global clock driver between the clock pin and the clkctrl block. I also try to drive the input pins of clkctrl by a clock buffer output (another clkctrl block ; path wold be pinà clkctrl(buffer)àclkctrl(mux)). But it seems that this is illegal. Can someone guide me with this? Thanks, Vittal
What device? Go to the handbook and into the Clock Network -> Clock Control Block section, and there should be a picture. There are two muxes into the global, one that is static based on configuration bits(although this one has the most flexibility) and one that is dynamic. So for Arria 10, the dynamic one can only switch between PLL outputs. For Cylone V, it's PLL outputs and one dedicated clock input pin. I don't think any of the dynamic inputs can be driven by a global(which is how another altclkctrl would feed into it).
Can you tell me which version of Quartus are you using? I am targeting it to use it for Arria 10 but I am unable to find it in the IP catalogue in Quartus 16.1
I have 16.1 open for a Cyclone V project, and was able to find ALTCLKCRL under Basic Functions -> Clocks, PLLs and Resets. It's right above the "Altera PLL" IP.
Standard, as Cyclone V is not in Pro.I believe you launched QSYS, which is for creating avalon fabric systems. The altclkctrl block is not avalon compliant and not available there. It only shows up in stand-alone IP. Go to View-> Utility Windows -> IP Catalog(or click Alt+7) in the main Quartus window, and you should find it there.
And when they converted all IP to use the "QSYS" interface, which makes sense from a maintenance and consistency perspective, it is confusing that there is IP for "QSYS Systems" and then stand-alone "IP Variants".
Altera PLL and altclkctrl should be different IP. (Although all PLLs drive globals, and the only way to get onto a global is through an altclkctrl, so their "implied" when you put down a PLL and you'll see them in the clock path details of a timing report, but if you want control of it you have to instantiate it, and it replaces the implied one.)
Hi Rysc,Sorry, I missed out on this thread as I was working on different things since quite some time. My apologies for the late response. I am using Cyclone-V, and as you suggested I looked at the device handbook. - https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf In the clock control section, I see that inclk0, inclk1 can be driven by a dedicated clock pin, and inclk2,inclk3 can be driven by PLL outputs (depending on the counter# and placement coordinates of PLL). I fed the clock coming from a dedicated clock pin (to inclk0) and PLL output - counter4 (to inclk2) to the CLKCTRL block. I used chip planner to double check that the PLL is to the left side of cyclone V device. However, I still get the same placement error of the fitter not being able to place a global clock driver between the clock pin and the clkctrl block. Do you think I am doing anything wrong here? Your help is appreciated. Thanks, Vittal