Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15548 Discussions

Altera Quartus: Compilation Problem

Altera_Forum
Honored Contributor II
1,380 Views

Hi,  

 

I am using Altera Quartus Web Edition 15. No issues in Synthesis process [done 100%] then after starting Compilation it`s processing is keep on going for endless. No Compilation Error Message but Compilation is keep on processing without termination. What is the issue. Please look over the attachment.
0 Kudos
6 Replies
Altera_Forum
Honored Contributor II
163 Views

Hi, 

It depends on system resources and design also check warning messages & try to resolve it, especially core related warning messages & enable parallel compilation. 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards  

Vikas Jathar  

 

Intel Customer Support – Engineering 

(Under Contract to Intel)
Altera_Forum
Honored Contributor II
163 Views

Is your project saved on a network drive? (e.g. \\domain\some\remote\drive) I've seen this sort of behaviour when UNC paths (such as the example give) and used for projects. Quartus will simply sit there pretending to compile but really doing nothing. No errors, no notifications.

Altera_Forum
Honored Contributor II
163 Views

I am getting the foll0wing critical warning messages. Whether that critical warning messages make compilation process to fail.  

 

Critical Warning (12887): Too many 2.5-V SE IO in bank 7A with LVDS RX pin DIFF_CLK_IN[0]. Reduce the number of 2.5-V I/Os used and re-run the analysis again. Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of SSN for the following SE I/O pins does not exceed 100%. 

 

Critical Warning (12887): Too many 2.5-V SE IO in bank 4A with LVDS RX pin DIFF_CLK_IN[1]. Reduce the number of 2.5-V I/Os used and re-run the analysis again. Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of SSN for the following SE I/O pins does not exceed 100%. 

 

Critical Warning (12887): Too many 2.5-V SE IO in bank 4A with LVDS RX pin DIFF_CLK_IN[2]. Reduce the number of 2.5-V I/Os used and re-run the analysis again. Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of SSN for the following SE I/O pins does not exceed 100%.
Altera_Forum
Honored Contributor II
163 Views

How large is your design and how long are you waiting? The Fitter can take a long time (many hours) for large complex designs and not post any messages for certain stages. As long as the timer in the lower right corner is still going, the program has not crashed, it's just chugging through your design. 

 

Those warnings won't affect compilation time, but you should follow the recommendation to avoid potential SSN issues.
Altera_Forum
Honored Contributor II
163 Views

 

--- Quote Start ---  

How large is your design and how long are you waiting? The Fitter can take a long time (many hours) for large complex designs and not post any messages for certain stages. As long as the timer in the lower right corner is still going, the program has not crashed, it's just chugging through your design. 

 

Those warnings won't affect compilation time, but you should follow the recommendation to avoid potential SSN issues. 

--- Quote End ---  

 

 

Thanks for your response :( 

 

I nearly waited for one hour, the compilation was in process.  

What is SSN issue ?How to sort it out ?
Altera_Forum
Honored Contributor II
163 Views

Simultaneous switching noise. You have too many pins close together that could all switch simultaneously causing a "victim" pin or pins to exhibit a voltage level switch. Search for "ssn" on altera.com to learn more about this.

Reply