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Altera_Forum
Honored Contributor I
736 Views

An issue with signal tapping using SignalTapII analyser

Hi, 

 

I want to tap and analyse the bits coming out of ADC to the FPGA in my board. 

I have declared all the bits as a signal in the code. 

 

But in the nodelist of SignalTapII pre-synthesis, some of the declared signals  

are not appearing. Instead of signals, if I define those bits as I/O, then it is visible in the nodelist so that I can tap those bits using signaltapII. But I don't have enough unused I/Os on the board.What could be the possible reason for that? Iam stuck because 

of this issue:( . Please help. :confused:
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3 Replies
Altera_Forum
Honored Contributor I
44 Views

Try using the "SignalTap II: post-fitting" Node Finder filter. 

 

Quartus might have created names that are similar to but slightly different from what you have in your source file. Usually the difference is at the end of the name. Try putting a wildcard at the end of the node name in the Node Finder.
Altera_Forum
Honored Contributor I
44 Views

Thanks for ur consideration. I have tried all that u suggested, but still I cannot find the  

name of the signal in place aforesaid. 

But I have one doubt regarding memory issue. Can the allocation of memory, for declaration of these values as a signals, create the problem?
Altera_Forum
Honored Contributor I
44 Views

Do the signals go anywhere once inside the chip. Any signal that doesn't eventually feed an output will be trimmed away by the optimizer and disappears. If necessary, just tie all the lines to a multi-input AND gate and feed this to a single dummy output.

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