Any approach to close clock toggle?

[Altera_Forum]

For a design, if I want to reduce power consumption, one approach is pausing the clock toggle for a module which does not need to work in a specific period. In the design, I can use a AND gate whose inputs are clk and enable as: 

 assign clkin=clk&&enable;  but with this AND gate, the clock skew may be more serious and it will be more difficult to analyse. So I wonder whether there is a better approach to close the clock toggle but don't use the AND gate?  Thanks.

[Altera_Forum]

Foreword: 

A purely combinational clock gating scheme like that can also suffer from glitches. If you really really need to use logic to gate clocks, use a module such as this: http://quartushelp.altera.com/9.1/mergedprojects/verify/da/comp_file_rules_clock.htm  That said, it's usually best not use logic to gate clocks in FPGAs due to skew issues.  Option 1: Use ALTCLKCTRL blocks.  These exist at the top of the clock distribution networks and provide glitch free gating without skew penalty -- they're always there, weather you're using them or not. Advanatge: you'll save power on everything, including the clock distribution tree itself Drawback: you're limited by the number of clock trees you have in the FPGA.  Option 2: Use clock enables Advantage: easy to use, no restrictions on number of enabled clocks Disadvantage: the clock distribution network into the LABs will still draw power.  always @ (posedge clk, posedge reset) begin if (reset) then // reset else if (enable) then // normal logic end  And in general, read the Quartus Handbook chapter on power optimization.

[Altera_Forum]

--- Quote Start ---  For a design, if I want to reduce power consumption, one approach is pausing the clock toggle for a module which does not need to work in a specific period. In the design, I can use a AND gate whose inputs are clk and enable as:   assign clkin=clk&&enable;   but with this AND gate, the clock skew may be more serious and it will be more difficult to analyse. So I wonder whether there is a better approach to close the clock toggle but don't use the AND gate?   Thanks.  --- Quote End ---     Use a PLL and hold the PLL in reset.   Also, before you get too creative, try an example design to see just how much power you may save. With the clock gating using gates, the extra power you burn while the design is running can easily overwhelm the savings you think you get when it is off. The reason is that by using non-global resources for distributing a clock you're charging and discharging far more capacitance that you would if you left the clock free running to each load on low capacitance routing.   Kevin Jennings

[Altera_Forum]

Thanks very much. I just wonder what is the definition of clock tree? I always see it but don't understand very well. Is the specific wire inside FPGA for clock signal? How can I know whether the clock tree is enough for my design? 

 Thanks.

[Altera_Forum]

Thanks very much. Do you mean I can use the PowerPlay Power Analyzer in Quartus II to do power estimation? 

 Thanks

[Altera_Forum]

--- Quote Start ---  Thanks very much. I just wonder what is the definition of clock tree? I always see it but don't understand very well. Is the specific wire inside FPGA for clock signal? How can I know whether the clock tree is enough for my design?  --- Quote End ---    No. A single clock buffer can't drive to all the flip-flops, memory blocks and etc in a chip -- the load would be too big. So, you need a tree: one clock buffer drives a few clock buffers, each of them drives a few more, etc, etc, until at the end you have the capability to drive every flip-flop and etc in the chip.  The FPGAs have several such clock trees and any of the global clock trees can drive the entire FPGA. If you only have one clock, then you only use one of those trees. But if you have multiple clocks or you're gating/muxing clocks using multiple ALTCLKCTRL blocks, then you'll use multiple clock trees.

[Altera_Forum]

Thanks, very helpful! Do I need to consider whether clock tree is enough when I design my system?

[Altera_Forum]

--- Quote Start ---  Thanks, very helpful! Do I need to consider whether clock tree is enough when I design my system?  --- Quote End ---   You don't need to consider the 'clock tree' at all. You have control over the signals and functions in a design. When you design something where you depend on a edge of a signal, it becomes a 'clock'. Whether or not a single buffer or multiple buffers are used to drive that clock is an implementation detail of the synthesis tool.   If you generate gated clocks (i.e. my_clock <= free_clock and some_signal; then you will have to deal with the consequences that will show up in the timing analysis report...regardless of how many buffers are used.   To answer your earlier question, yes you would use the Quartus power analyzer tool to determine estimated power consumption.   Kevin Jennings

[Altera_Forum]

Thanks very much, Kevin. They are very helpful!