Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16339 Discussions

Are there any plans to update the Cyclone 10 GX dev board collateral kit to work with recent versions of Quartus?


I'm trying to build the simple_socket_server example from the Cyclone 10 GX dev board collateral, w/o modifications and I get the error:

The reference clock on PLL "sss_qsys_inst|tse_0_tse|tse_mac|i_lvdsio_rx_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.


I can't upgrade the IP because the IP upgrade fails, and leaves the project in a state that does not work.


This error looks like it was introduced in 18.1, but clearly the dev kit collateral has not been updated to address this.


Or are you abandoning supporting the Cyclone 10 GX dev board?

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4 Replies

Hi JGurn,


May i know are you using platform designer? Can you try to open platform designer in Quartus and upgrade the IP there? Some user might have this issue to upgrade the IP in Quartus.




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Hi SooYL, JGurn,


I've encountered the same problem with Cyclone 10 GX as well as with Arria 10 GX and i think there is a problem with Quartus Prime Pro 18.1.

I use TSE with LVDS Phy. Please see my pin planner screenshot for Arria 10 GX DevKit attached (The same thing for Cyclone 10 GX)

The reference clock is definitely in the same bank with rx and tx lines. But Quartus Pro 18.1 fitter says that it is not

Here are assignments for eth_ref_clk:

   eth_ref_clk   Location   PIN_BD24   Yes      

   eth_ref_clk   I/O Standard   LVDS   Yes   system_top   

   eth_ref_clk   Input Termination   Differential   No   system_top   

   eth_ref_clk   Global Signal   Global Clock   Yes   system_top   


Quartus 17.1 and 18.0 fitter finishes with no errors.


Qsys gives this warning:

system_bd_sys_ethernet.sys_ethernet: To prevent potential performance issues, please ensure the reference clock to the LVDS uses the dedicated reference clock input within the same I/O bank directly. Manual reference clock promotion is not recommended

May be we can perform manual clock promotion in this case? How can we do this?



if you have the same problems as me with TSE core on cyclone 10 gx dev board the answer is in topic "lvds serdes reference clock enforcement change in 181":


It's the very bad practice that came from brand x land where you can't change the version of the tool without a lot of the physical pain. (When you do a lot of the extra hours and have the physical pain).

It was so nice that in the past if was possible to go to the newer or older(!) version of Qaurtus and now when you try to escape the hell with brand x but it still comes after you.


Altera had the very good practice when engineers who did Quartus used it for the real projects themself.

(I remember the funny case when one brand x fanboy tried to use brand x badware and just said: "Did they tried to use it themself"?)

For me it's very sad to see that intel missed the very good practice from Altera and takes on board the bad practices from the horrible brand x.


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Somehow screenshot haven't been attached in the previous post.

Attaching it again.

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